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december 2010 i ? 2010 microsemi corporation smartfusion intelligent mixed signal fpgas microcontroller subsystem (mss) ? hard 100 mhz 32-bit arm ? cortex?-m3 ? 1.25 dmips/mhz throughput from zero wait state memory ? memory protection unit (mpu) ? single cycle multiplication, hardware divide ? jtag debug (4 wires), serial wire debug (swd, 2 wires), and single wire viewer (swv) interfaces ? internal memory ? embedded nonvolatile flash memory (envm), 128 kbytes to 512 kbytes ? embedded high-speed sram (esram), 16 kbytes to 64 kbytes, implement ed in 2 physical blocks to enable simultaneous access from 2 different masters ? multi-layer ahb communications matrix ? provides up to 16 gbps of on-chip memory bandwidth, 1 allowing multi-master schemes ? 10/100 ethernet mac with rmii interface 2 ? programmable external me mory controller, which supports: ? asynchronous memories ? nor flash, sram, psram ? synchronous srams ?two i 2 c peripherals ? two 16550 compatible uarts ? two spi peripherals ? two 32-bit timers ? 32-bit watchdog timer ? 8-channel dma controller to offload the cortex-m3 from data transactions ? clock sources ? 32 khz to 20 mhz main oscillator ? battery-backed 32 khz low power oscillator with real-time counter (rtc) ? 100 mhz embedded rc oscillator; 1% accurate ? embedded analog pll with 4 output phases (0, 90, 180, 270) high-performance fpga ? based on proven proasic ? 3 fpga fabric ? low power, firm-error immune 130-nm, 7-layer metal, flash-based cmos process ? nonvolatile, live at power-up, retains program when powered off ? 350 mhz system performance ? embedded srams and fifos ? variable aspect ratio 4,608-bit sram blocks ? x1, x2, x4, x9, and x18 organizations ? true dual-port sram (excluding x18) ? programmable embedded fifo control logic ? secure isp with 128-bit aes via jtag ? flashlock ? to secure fpga contents ? five clock conditioning circuits (cccs) with up to 2 integrated analog plls ? phase shift, multiply/div ide, and delay capabilities ? frequency: input 1.5?350 mhz, output 0.75 to 350 mhz programmable analog analog front-end (afe) ? up to three 12-bit sar adcs ? 500 ksps in 12-bit mode ? 550 ksps in 10-bit mode ? 600 ksps in 8-bit mode ? internal 2.56 v reference or optional external reference ? one first-order ? dac (sigma-delta) per adc ? 12-bit 500 ksps update rate ? up to 5 high-performance analog signal conditioning blocks (scb) per device, each including: ? two high-voltage bipolar voltage monitors (with 4 input ranges from 2.5 v to ?11.5/+14 v) with 1% accuracy ? high gain current monitor, differential gain = 50, up to 14 v common mode ? temperature monitor (resolution = ?c in 12-bit mode; accurate from ?55c to 150c) ? up to ten high-speed voltage comparators (t pd =15ns) analog compute engine (ace) ? offloads cortex-m3?based mss from analog initialization and processing of adc, dac, and scbs ? sample sequence engine for adc and dac parameter set-up ? post-processing engine for functions such as low- pass filtering and linear transformation ? easily configured via gui in libero ? integrated design (ide) software i/os and operating voltage ? fpga i/os ? lvds, pci, pci-x, up to 24 ma i oh /i ol ? up to 350 mhz ? mss i/os ? schmitt trigger, up to 6 ma i oh , 8 ma i ol ? up to 180 mhz ? single 3.3 v power supply with on-chip 1.5 v regulator ? external 1.5 v is allowed by bypassing regulator (digital vcc = 1.5 v for fpga and mss, analog vcc = 3.3 v and 1.5 v) 1 theoretical maximum 2 a2f200 and larger devices revision 5
smartfusion intelligent mixed signal fpgas ii revision 5 smartfusion family product table smartfusion device a2f060 1 a2f200 a2f500 fpga fabric system gates 60,000 200,000 500,000 tiles (d-flip-flops) 1,536 4,608 11,520 ram blocks (4,608 bits) 8 8 24 microcontroller subsystem (mss) flash (kbytes) 128 256 512 sram (kbytes) 16 64 64 cortex-m3 with memory protection unit (mpu) yes 10/100 ethernet mac no yes external memory controller (e mc) 24-bit address,16-bit data dma 8 ch i 2 c 2 spi 2 16550 uart 2 32-bit timer 2 pll 1 1 2 3 32 khz low power oscillator 1 100 mhz on-chip rc oscillator 1 main oscillator (32 khz to 20 mhz) 1 programmable analog adcs (8-/10-/12-bit sar) 1 2 3 4 dacs (12-bit sigma-delta) 1 2 3 4 signal conditioning blocks (scbs) 1 4 5 4 comparators 2 28 10 4 current monitors 2 14 5 4 temperature monitors 2 14 5 4 bipolar high voltage monitors 2 28 10 4 notes: 1. under definition; subject to change. 2. these functions share i/o pins and may not all be available at the same time. see the analog front-end overview section in the smartfusion programmable analog user?s guide for details. 3. two plls are available in cs288 and fg484 (one pll in fg256). 4. available on fg484 only. fg256 and cs288 packages offer the same programmable analog capabilities as a2f200.
smartfusion intelligent mixed signal fpgas revision 5 iii package i/os: mss + fpga i/os smartfusion device status device a2f060 a2f200 a2f500 package fg256 cs288 fg256 fg484 cs288 fg256 fg484 direct analog input 6 8 8 8 8 8 12 total analog input 10 24 24 24 24 24 32 total analog output 1 2 2 2 2 2 3 mss i/os 1,2 25 31 25 41 31 25 41 fpga i/os 66 78 66 94 78 66 128 total i/os 102 135 117 161 135 117 204 notes: 1. 16 mss i/os are multiplexed and can be used as fpga i/os, if not needed for mss. these i/os support schmitt triggers and support only lvttl and lvcmos (1.5 / 1.8 / 2.5, 3.3 v) standards. 2. 9 mss i/os are primarily for 10/100 ethernet mac and are also multiplexed and can be used as fpga i/os if ethernet mac is not used in a design. these i/os suppo rt schmitt triggers and support only lv ttl and lvcmos (1.5 / 1.8 / 2.5, 3.3 v standards. device status a2f060 advance a2f200 production a2f500 production
smartfusion intelligent mixed signal fpgas iv revision 5 smartfusion block diagram legend : sdd ? sigma-delta dac scb ? signal conditioning block pdma ? peripheral dma iap ? in-application programming abps ? active bipolar prescaler wdt ? watchdog timer swd ? serial wire debug microcontroller subsystem programmable analog fpga fabric sram sram sram sram sram sram sysreg envm 10/100 emac esram timer2 timer1 apb i 2 c 2 uart 2 spi 2 dac (sdd) dac (sdd) ppb ........ ........ ............ versatiles 3 v i 2 c 1 uart 1 spi 1 iap pdma apb emc ahb bus matrix efrom apb sample sequencing engine post processing engine adc analog compute engine pll supervisor wdt osc 32 khz rc + ? rtc jtag cortex ? -m3 swd nvic systick mpu sd i volt mon. ( abps ) temp. mon. scb curr. mon. comparator adc volt mon. ( abps ) temp. mon. scb curr. mon. comparator 3 v ............ ....
smartfusion intelligent mixed signal fpgas revision 5 v smartfusion system architecture note: architecture for a2f500 bank 4 bank 5 bank 0 bank 3 bank 1 bank 2 pll/ccc mss fpga analog isp aes decryption charge pumps embedded nvm (envm) cortex-m3 microcontroller subsystem (mss) embedded sram (esram) embedded flashrom (efrom) scb scb adc and dac adc and dac scb scb osc. ccc
smartfusion intelligent mixed signal fpgas vi revision 5 product ordering codes temperature grade offerings note: *most devices in the smartfusion family can be ordered with the y suffix. devices wi th a package size greater or equal to 5x5 mm are supported. contact your local microsemi soc pr oducts group sales representative for more information. smartfusion devices a2f060 a2f200 a2f500 cs288 ? c, i c, i fg256 c, i c, i c, i fg484 ? c, i c, i notes: 1. c = commercial temperature range: 0c to 85c junction 2. i = industrial temperature range: ?40c to 100c junction a2f200 fg _ part number smartfusion devices speed grade ?1 = 100 mhz mss speed; fpga fabric 15% faster than standard = 80 mhz mss speed; fpga fabric at standard speed cpu type m3 m3 = cortex-m3 package type 484 i g package lead count 256 288 484 application (junction temperature range) y security feature* y = device includes license to implement ip based on the cryptography research, inc. (cri) patent portfolio blank = commercial (0 to +85c) i = industrial (?40 to +100c) es = engineering silicon (room temperature only) 200,000 system gates a2f200 = 60,000 system gates a2f060 = 500,000 system gates a2f500 = fg = fine pitch ball grid array (1.0 mm pitch) cs = chip scale package (0.5 mm pitch) f envm size a = 8 kbytes b = 16 kbytes c = 32 kbytes d = 64 kbytes e = 128 kbytes f = 256 kbytes g = 512 kbytes lead-free packaging options h = halogen-free packaging g = rohs-compliant (green) packaging blank = standard packaging 1 blank
smartfusion intelligent mixed signal fpgas revision 5 table of contents smartfusion device family overview introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 smartfusion dc and swit ching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 main and lower power crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 clock conditioning circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 fpga fabric sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 embedded nonvolatile memory block (envm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 embedded flashrom (efrom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 programmable analog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 serial peripheral interface (spi) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86 inter-integrated circuit (i 2 c) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 smartfusion development tools smartfusion ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 software integrated design environment (i de) choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 operating system and middleware support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 smartfusion programming in-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 in-application programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 typical programming and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 pin descriptions supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 user-defined supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 user pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 special function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 microcontroller subsystem (mss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 analog front-end (afe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 analog front-end pin-level function multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 288-pin csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 256-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 484-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
table of contents revision 5 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 microsemi soc products group safety critic al, life support, and high-reliability applications policy . . . . . . . . . . 6-7
revision 5 1-1 1 ? smartfusion device family overview introduction the smartfusion family of intelligent mixed signal fp gas builds on the technology first introduced with the fusion mixed signal fpgas. smartfusion de vices are made possible by integrating fpga technology with programmable high-performance analog and hardened arm ? cortex?-m3 microcontroller blocks on a flash semiconductor proces s. the smartfusion family takes its name from the fact that these three discrete technologies are integrated on a si ngle chip, enabling the lowest cost of ownership and smallest footprint solution to you. general description microcontroller subsystem (mss) the mss is composed of a 100 mhz cortex-m3 processor and integrated peripherals, which are interconnected via a multi-layer ahb bus matrix (ab m). this matrix allows the cortex-m3 processor, fpga fabric master, ethernet mess age authentication controller (mac), when available, and peripheral dma (pdma) controller to act as masters to the integrated peripherals, fpga fabric, embedded nonvolatile memory (envm), embedded synchronou s ram (esram), external memory controller (emc), and analog compute engine (ace) blocks. smartfusion devices of different densities offer va rious sets of integrated peripherals. available peripherals include spi, i 2 c, and uart serial ports, embedded fl ashrom (efrom), 10/100 ethernet mac, timers, phase-locked loops (p lls), oscillators, real-time counters (rtc), and peripheral dma controller (pdma). programmable analog analog front-end (afe) smartfusion devices offer an enhanced analog front-end compared to fusion devices. the successive approximation register analog-to-digital converters (sar adc) are similar to those found on fusion devices. smartfusion also adds first order sigma- delta digital-to-analog converters (sdd dac). smartfusion can handle multiple analog signals simultaneously with its signal conditioning blocks (scbs). scbs are made of a combination of active bipolar prescalers (abps), comparators, current monitors and temperature monitors. abps modules allo w larger bipolar voltages to be fed to the adc. current monitors take the voltage across an external sense resistor and convert it to a voltage suitable for the adc input range. similarly, the temperature monitor reads the current through an external pn- junction (diode or transistor) and converts it interna lly for the adc. the scb also includes comparators to monitor fast signal thresholds without using the a dc. the output of the comparators can be fed to the analog compute engine or the adc. analog compute engine (ace) the mixed signal blocks found in sm artfusion are cont rolled and connecte d to the rest of the system via a dedicated processor called the anal og compute engine (ace). the role of the ace is to offload control of the analog blocks from the cortex-m3, thus offering faster throughput or better power consumption compared to a system where the main processor is in charge of moni toring the analog resources. the ace is built to handle sampling, sequencing, and post-processing of the adcs, dacs, and scbs.
smartfusion device family overview 1-2 revision 5 proasic3 fpga fabric the smartfusion family, based on the prov en, low power, firm-erro r immune proasic ? 3 flash fpga architecture, benefits from the advantages only flash-based devices offer: reduced cost of ownership advantages to the designer extend beyond low unit cost, high performance, an d ease of use. flash- based smartfusion devices are live at power-up and do not need to be loaded from an external boot prom at each power-up. on-board security me chanisms prevent access to the programming information and enable secure remote updates of th e fpga logic. designers can perform secure remote in-system programming (isp) to support future desig n iterations and critic al field upgrades, with confidence that valuable ip cannot be compromise d or copied. secure isp can be performed using the industry standard aes algorithm with mac data authenticati on on the device. low power flash-based smartfusion devices exhibit power characte ristics similar to those of an asic, making them an ideal choice for power-sensitive applications. with smartfusion devices, there is no power-on current and no high current transition, both of which are common with sram-based fpgas. smartfusion devices also have low dynamic powe r consumption and support very low power time- keeping mode, offering further power savings. security as the nonvolatile, flash-based smartfusion fami ly requires no boot prom, there is no vulnerable external bitstream. smartfusion devices incorporate flashlock ? , which provides a unique combination of reprogrammability and design security without ex ternal overhead, advantage s that only an fpga with nonvolatile flash programming can offer. smartfusion devices utilize a 128-bit flas h-based key lock and a separate aes key to secure programmed ip and configuration data. the flashr om data in fusion devices can also be encrypted prior to loading. additi onally, the flash memory blocks can be programmed during runtime using the aes- 128 block cipher encryption standard (fips publication 192). smartfusion devices with aes-based security allo w for secure remote field updates over public networks, such as the in ternet, and ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip thieves. as an a dditional security measure, the fpga configuration data of a programmed fusion device cannot be read back, although secure design verification is possible. during design, the user controls and defines both internal and external access to the flash memory blocks. security, built into the fpga fabric, is an inheren t component of the smartfus ion family. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremel y difficult. smartfusion with flas hlock and aes security is unique in being highly resistant to both invasive and noninvas ive attacks. your valuable ip is protected, making secure remote isp possible. a sm artfusion device provides the most impenetrable security for programmable logic designs. single chip flash-based fpgas store their configuration informati on in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga st ructure, and no external configuration data needs to be loaded at system power-up (unlike sram-based fpgas). therefore, fl ash-based smartfusion fpgas do not require system config uration components such as elec trically erasable programmable read-only memories (eeproms) or microcontrollers to load device configuration data during power-up. this reduces bill-of-materials co sts and pcb area, and increases system security and reliability. live at power-up flash-based smartfusion devices are live at po wer-up (lapu). lapu smartfusion devices greatly simplify total system design and reduce total system cost by eliminating the need for complex programmable logic devices (cplds). smartfusion lapu clocking (plls) replaces off-chip clocking resources. in addition, glitches and brownouts in system power will not corrup t the smartfusion device flash configuration. unlike sra m-based fpgas, the device will not have to be reloaded when system power is restored. this enables reduction or co mplete removal of expensive voltage monitor and
smartfusion intelligent mixed signal fpgas revision 5 1-3 brownout detection devices from the pcb design. flash-based smartfusion devices simplify total system design and reduce cost and design risk, while in creasing system reliability. immunity to firm errors firm errors occur most commonly when high-energy neutrons, generated in t he atmosphere, strike a configuration cell of an sram fpga. the energy of the collision can change the state of the configuration cell and thus change the logic, routing, or i/o config uration behavior in an unpredictable way. another source of radiation-induced firm errors is al pha particles. for alpha radiation to cause a soft or firm error, its source must be in very close proximit y to the affected circuit. the alpha source must be in the package molding compound or in the die itself. while low-alpha molding compounds are being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors. firm errors are impossible to prevent in sram fp gas. the consequence of this type of error can be a complete system failure. firm erro rs do not occur in smartfusion flash-based fpgas. once it is programmed, the flash cell config uration element of smartfusion fpgas cannot be altered by high energy neutrons and is therefore immune to errors from them. recoverable (or soft) errors occur in the user data srams of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric.

revision 5 2-1 2 ? smartfusion dc and switching characteristics general specifications operating conditions stresses beyond the operating conditions listed in table 2-1 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the recommended o perating conditions specified in table 2-3 on page 2-3 is not implied. table 2-1 ? absolute maximum ratings symbol parameter limits units vcc dc core supply voltage ?0.3 to 1.65 v vjtag jtag dc voltage ?0.3 to 3.75 v vpp programming voltage ?0.3 to 3.75 v vccpllx analog power supply (pll) ?0.3 to 1.65 v vccfpgaiobx dc fpga i/o buffer supply voltage ?0.3 to 3.75 v vccmssiobx dc mss i/o buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (vccxxxxiobx + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot- insertion mode is disabled) v vcc33a analog clean 3.3 v supply to the analog circuitry ?0.3 to 3.75 v vcc33adcx analog 3.3 v supply to adc ?0.3 to 3.75 v vcc33ap analog clean 3.3 v supply to the charge pump ?0.3 to 3.75 v vcc33sddx analog 3.3 v supply to th e sigma-delta dac ?0.3 to 3.75 v varefx voltage reference for adc 1.0 to 3.75 v vccrcosc analog supply to the inte grated rc oscillator ?0.3 to 3.75 v vddbat external battery supply ?0.3 to 3.75 v vccmainxtal analog supply to the main crystal oscillator ?0.3 to 3.75 v vcclpxtal analog supply to the low power 32 khz crystal oscillator ?0.3 to 3.75 v vccenvm embedded nonvolatile me mory supply ?0.3 to 1.65 v vcc15a analog 1.5 v supply to the analog circuitry ?0.3 to 1.65 v vcc15adcx analog 1.5 v supply to the adc ?0.3 to 1.65 v note: the device should be operated within the limits specifi ed by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 2-5 on page 2-4 .
smartfusion dc and switching characteristics 2-2 revision 5 table 2-2 ? analog maximum ratings parameter conditions min. max. units abps[n] pad voltage (relative to ground) gdec[1:0] = 00 (15.36 v range) absolute maximum ?11.5 14.4 v recommended ?11 14 v gdec[1:0] = 01 (10.24 v range) ?11.5 12 v gdec[1:0] = 10 (5.12 v range) ?6 6 v gdec[1:0] = 11 (2.56 v range) ?3 3 v cm[n] pad voltage relative to ground) cmb_di_on = 0 (adc isolated) comp_en = 0 (comparator off, for the associated even-numbered comparator) absolute maximum ?0.3 14.4 v recommended ?0.3 14 v cmb_di_on = 0 (adc isolated) comp_en = 1 (comparator on) ?0.3 3 v tmb_di_on = 1 (direct adc in) ?0.3 3 v tm[n] pad voltage (relative to gr ound) tmb_di_on = 0 (adc isolated) comp_en = 1(comparator on) ?0.3 3 v tmb_di_on = 1 (direct adc in) ?0.3 3 v adc[n] pad voltage (relative to ground) ?0.3 3.6 v
actel smartfusion intelligent mixed signal fpgas revision 5 2-3 table 2-3 ? recommended operating conditions symbol parameter 1 commercial industrial units t j junction temperature 0 to +85 ?40 to +100 c vcc 2 1.5 v dc core supply voltage 1.425 to 1.575 1.425 to 1.575 v vjtag jtag dc voltage 1.425 to 3.6 1.425 to 3.6 v vpp programming voltage programming mode 3.15 to 3.45 3.15 to 3.45 v operation 3 0 to 3.6 0 to 3.6 v vccpllx analog power supply (pll) 1.425 to 1.575 1.425 to 1.575 v vccfpgaiobx/ vccmssiobx 4 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds differential i/o 2.375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3.0 to 3.6 3.0 to 3.6 v vcc33a 5 analog clean 3.3 v supply to the analog circuitry 3.15 to 3.45 3.15 to 3.45 v vcc33adcx 5 analog 3.3 v supply to adc 3.15 to 3.45 3.15 to 3.45 v vcc33ap 5 analog clean 3.3 v supply to the char ge pump 3.15 to 3.45 3.15 to 3.45 v vcc33sddx 5 analog 3.3 v supply to sigma-delta dac 3.15 to 3.45 3.15 to 3.45 v varefx voltage reference for adc 2.527 to 3.3 2.527 to 3.3 v vccrcosc analog supply to the integrated rc oscillator 3.15 to 3.45 3.15 to 3.45 v vddbat external battery supply 2.7 to 3.63 2.7 to 3.63 v vccmainxtal 5 analog supply to the main crystal o scillator 3.15 to 3.45 3.15 to 3.45 v vcclpxtal 5 analog supply to the low power 32 khz crystal oscillator 3.15 to 3.45 3.15 to 3.45 v vccenvm embedded nonvolatile memory supply 1.425 to 1.575 1.425 to 1.575 v vcc15a 2 analog 1.5 v supply to the analog circuitry 1.425 to 1.575 1.425 to 1.575 v vcc15adcx 2 analog 1.5 v supply to the adc 1.425 to 1.575 1.425 to 1.575 v notes: 1. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 2. the following 1.5 v supplies should be connected together while following proper noise filtering practices: vcc, vcc15a, and vcc15adcx. 3. vpp can be left floating during operation (not programming mode). 4. the ranges given here are for power s upplies only. the recommended input voltage ranges specific to each i/o standard are given in table 2-18 on page 2-23 . vccxxxxiobx should be at the same voltage within a given i/o bank. 5. the following 3.3 v supplies should be connected together wh ile following proper noise filtering practices: vcc33a, vcc33adcx, vcc33ap, vcc33sddx, vccmainxtal, and vcclpxtal.
smartfusion dc and switching characteristics 2-4 revision 5 power supply sequencing requirement smartfusion devices have an on-chip 1.5 v regulator, but usage of an external 1.5 v supply is also allowed while the on-chip regulator is disabled. in that case, the 3.3 v supplies (vcc33a, etc.) should be powered before 1.5 v (vcc, etc.) supplies. the 1.5 v supplies should be enabled only after 3.3 v supplies reach a value higher than 2.7 v. i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is designed into every smartfusion ? device. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any sequ ence with minimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-6 . there are five regions to consider during power-up. smartfusion i/os are activated only if al l of the following three conditions are met: 1. vcc and vccxxxxiobx are above the minimum specified trip points ( figure 2-1 on page 2-6 ). 2. vccxxxxiobx > vcc ? 0.75 v (typical) table 2-4 ? fpga and embedded flash programming, storage and operating limits product grade storage temperature element grade programming cycles retention commercial min. t j = 0c fpga/flashrom 500 20 years min. t j = 85c embedded flash < 1,000 20 years < 10,000 10 years < 15,000 5 years industrial min. t j = ?40c fpga/flashrom 500 20 years min. t j = 100c embedded flash < 1,000 20 years < 10,000 10 years < 15,000 5 years table 2-5 ? overshoot and undershoot limits 1 vccxxxxiobx average vccxxxxiobx?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of si x clock cycles. if the overshoot/unders hoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v. 3. this table does not provide pci overshoot/undershoot limits.
actel smartfusion intelligent mixed signal fpgas revision 5 2-5 3. chip is in the soc mode. vccxxxxiobx trip point: ramping up: 0.6 v < trip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v vcc trip point : ramping up: 0.6 v < trip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v vcc and vccxxxxiobx ramp-up trip points are about 100 mv higher than ramp-down trip points. this specifically built-in hyster esis prevents undesirable power-up osc illations and current surges. note the following: ? during programming, i/os become tristated and weakly pulled up to vccxxxxiobx. ? jtag supply, pll power supplies, and charge pump vpump supply have no influence on i/o behavior. pll behavior at brownout condition the microsemi soc products group recommends usi ng monotonic power supplies or voltage regulators to ensure proper power-up behavior. power ramp -up should be monotonic at least until vcc and vccpllx exceed brownout activation levels. the vcc activation level is specified as 1.1 v worst-case (see figure 2-1 on page 2-6 for more details). when pll power supply voltage and/or vcc levels drop below the vcc brownout levels (0.75 v 0.25 v), the pll output lock signal goes low and/or the output clock is lost. refer to the "power-up/-down behavior of low power flash devices" chapter of the proasic3 fpga fabric user?s guide for information on clock and lock recovery. internal power-up activation sequence 1. core 2. input buffers output buffers, after 200 ns delay from input buffer activation
smartfusion dc and switching characteristics 2-6 revision 5 figure 2-1 ? i/o state as a function of vccxxxxiobx and vcc voltage levels vccxxxxiobx region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because vccxxxxiobx / v cc are below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. min vccxxxxiobx datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v vcc vcc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil , voh / vol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vccxxxxiobx region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vccxxxxiobx + vt
actel smartfusion intelligent mixed signal fpgas revision 5 2-7 thermal characteristics introduction the temperature variable in the soc products group designer software refers to the junction temperature, not the ambi ent, case, or board temp eratures. this is an im portant distinction because dynamic and static power consumption will cause the ch ip's junction temperature to be higher than the ambient, case, or board temperatures. eq 1 through eq 3 give the relationship between thermal resistance, temperature gradient, and power. eq 1 eq 2 eq 3 where ja = junction-to-air thermal resistance jb = junction-to-board thermal resistance jc = junction-to-case thermal resistance t j = junction temperature t a = ambient temperature t b = board temperature (measured 1.0 mm away from the package edge) t c = case temperature p = total power dissipated by the device table 2-6 ? package thermal resistance product die size ja jc jb units (mm) still air 1.0 m/s 2.5 m/s a2f200m3f-fg256 x = 4.0; y = 5.6 33.7 30.0 28.3 9.3 24.8 c/w a2f200m3f-fg484 x = 5.10; y = 7.3 21.8 18.2 16.7 7.7 16.8 c/w ja t j a ? p ------------------ = jb t j t b ? p ------------------ - = jc t j t c ? p ------------------- =
smartfusion dc and switching characteristics 2-8 revision 5 theta-ja junction-to-ambient thermal resistance ( ja ) is determined under standa rd conditions specified by jedec (jesd-51), but it has little relevance in actual performance of the product. it should be used with caution but is useful for comparing the th ermal performance of one package to another. a sample calculation showing the maximum power dissipation allowed for the a2f200-fg484 package under forced convection of 1.0 m/s and 75 c ambient temperature is as follows: eq 4 where eq 5 the power consumption of a device can be calcul ated using the microsemi soc products group power calculator. the device's power consumption must be lower than the calculated maximum power dissipation by the package. if the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be attached on to p of the case, or the airflow inside the system must be increased. theta-jb junction-to-board thermal resistance ( jb ) measures the ability of the pa ckage to dissipate heat from the surface of the chip to the pcb. as defined by t he jedec (jesd-51) standard, the thermal resistance from junction to board uses an isothermal ring cold plate zone concept. the ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. the cold plate is mounted on a jedec standard board with a minimum distanc e of 5.0 mm away from the package edge. theta-jc junction-to-case thermal resistance ( jc ) measures the ability of a devic e to dissipate heat from the surface of the chip to the top or bottom surface of the pa ckage. it is applicable for packages used with external heat sinks. constant temperature is applie d to the surface in consideration and acts as a boundary condition. this only applies to situations wher e all or nearly all of the heat is dissipated through the surface in consideration. calculation for heat sink for example, in a design implemented in an a2f200-fg484 package with 2.5 m/s airflow, the power consumption value using the power calcul ator is 3.00 w. the user-dependent t a and t j are given as follows: from the datasheet: ja = 19.00c/w (taken from table 2-6 on page 2-7 ). t a = 75.00c t j = 100.00c t a = 70.00c ja = 17.00c/w jc = 8.28c/w maximum power allowed t j(max) t a(max) ? ja --------------------------------------------- = maximum power allowed 100.00c 75.00c ? 19.00c/w ---------------------------------------------------- 1.3 w ==
actel smartfusion intelligent mixed signal fpgas revision 5 2-9 eq 6 the 1.76 w power is less than the required 3.00 w. the design therefore requires a heat sink, or the airflow where the device is mounted should be incr eased. the design's total junction-to-air thermal resistance requirement can be estimated by eq 7 : eq 7 determining the heat sink's thermal performance proceeds as follows: eq 8 where eq 9 a heat sink with a thermal resist ance of 5.01c/w or better should be used. thermal resistance of heat sinks is a function of airflow. the heat sink perfo rmance can be significantly improved with increased airflow. carefully estimating thermal resistance is important in the long-term reliability of an fpga. design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device. note: the junction-to-air and junction-to-board th ermal resistances are based on jedec standard (jesd-51) and assumptions made in building the model. it may not be realized in actual application and therefore should be used with a degree of caution. junction-to-case thermal resistance assumes that all power is dissipated through the case. temperature and voltage derating factors ja = 0.37c/w = thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer sa = thermal resistance of the heat sink in c/w table 2-7 ? temperature and voltage derati ng factors for timing delays (normalized to t j = 85c, worst-case vcc = 1.425 v) array voltage vcc (v) junction temperature (c) ?40c 0c 25c 70c 85c 100c 1.425 0.86 0.91 0.93 0.98 1.00 1.02 1.500 0.81 0.86 0.88 0.93 0.95 0.96 1.575 0.78 0.83 0.85 0.90 0.91 0.93 p t j t a ? ja ------------------ - 100c 70c ? 17.00 w ----------------------------------- - 1.76 w == = ja(total) t j t a ? p ------------------ - 100c 70c ? 3.00 w ----------------------------------- - 10.00c/w == = ja(total) jc cs sa ++ = sa ja(total) jc ? cs ? = sa 13.33c/w 8.28c/w ? 0.37c/w ? 5.01c/w ==
smartfusion dc and switching characteristics 2-10 revision 5 calculating power dissipation quiescent supply current power per i/o pin table 2-8 ? quiescent supply current characteristics power supplies configuration modes and power supplies vccxxxxiobx vccfpgaiobx vccmssiobx vcc33a / vcc33adcx vcc33ap / vcc33sddx vccmainxtal / vcclpxtal vcc / vcc15a / vcc15adcx vccpllx / vcomplax vccenvm vddbat vccrcosc vjtag vpp envm (reset/off) lpxtal (enable/disable) mainxtal (enable/disable) time keeping mode 0 v 0 v 0 v 3.3 v 0 v 0 v 0 v off enable disable standby mode on 1 3.3 v 1.5 v n/a 3.3 v n/a n/a reset enable disable parameter modes a2f200 a2f500 1.5 v domain 3.3 v domain 2 1.5 v domain 3.3 v domain 2 idc1 time keeping mode n/a 10 a n/a 10 a idc2 standby mode 3 ma 1 ma tbd 1 ma notes: 1. on means proper voltage is applied. refer to table 2-3 on page 2-3 for recommended operating conditions. 2. current monitors and temperature monitors should not be used when power-down and/or sleep mode are required by the application. table 2-9 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings applicable to fpga i/o banks vccfpgaiobx (v) static power pdc7 (mw) dynamic power pac9 (w/mhz) single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.22 2.5 v lvcmos 2.5 ? 4.65 1.8 v lvcmos 1.8 ? 1.65 1.5 v lvcmos (jesd8-11) 1.5 ? 0.98 3.3 v pci 3.3 ? 17.64 3.3 v pci-x 3.3 ? 17.64 differential lvds 2.5 2.26 0.83 lvpecl 3.3 5.72 1.81
actel smartfusion intelligent mixed signal fpgas revision 5 2-11 table 2-10 ? summary of i/o input buffer power (per pin) ? default i/o software settings applicable to mss i/o banks vccmssiobx (v) static power pdc7 (mw) dynamic power pac9 (w/mhz) single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 17.21 3.3 v lvcmos / 3.3 v lvcmos ? schmitt trigger 3.3 ? 20.00 2.5 v lvcmos 2.5 ? 5.55 2.5 v lvcmos ? schmitt trigger 2.5 ? 7.03 1.8 v lvcmos 1.8 ? 2.61 1.8 v lvcmos ? schmitt trigger 1.8 ? 2.72 1.5 v lvcmos (jesd8-11) 1.5 ? 1.98 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 ? 1.93 table 2-11 ? summary of i/o output bu ffer power (per pin) ? de fault i/o software settings * applicable to fpga i/o banks c load (pf) vccfpgaiobx (v) static power pdc8 (mw) dynamic power pac10 (w/mhz) single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 468.67 2.5 v lvcmos 35 2.5 ? 267.48 1.8 v lvcmos 35 1.8 ? 149.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 103.12 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 differential lvds ? 2.5 7.74 89.82 lvpecl ? 3.3 19.54 167.55 note: *dynamic power consumption is given for standard l oad and software default drive strength and output slew. table 2-12 ? summary of i/o output bu ffer power (per pin) ? de fault i/o software settings applicable to mss i/o banks c load (pf) vccmssiobx (v) static power pdc8 (mw) 2 dynamic power pac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 10 3.3 ? 155.65 2.5 v lvcmos 10 2.5 ? 88.23 1.8 v lvcmos 10 1.8 ? 45.03 1.5 v lvcmos (jesd8-11) 10 1.5 ? 31.01
smartfusion dc and switching characteristics 2-12 revision 5 power consumption of various internal resources table 2-13 ? different components contributing to dynamic power consumption in smartfusion devices parameter definition power supply device units name domain a2f500 a2f200 pac1 clock contribution of a global rib vcc 1.5 v 5.0 9.3 w/mhz pac2 clock contribution of a global spine vcc 1.5 v 2.5 0.8 w/mhz pac3 clock contribution of a versatile row vcc 1.5 v 1.1 0.81 w/mhz pac4 clock contribution of a versatile used as a sequential module vcc 1.5 v 0.1 0.11 w/mhz pac5 first contribution of a versatile used as a sequential module vcc 1.5 v 0.07 w/mhz pac6 second contribution of a versatile used as a sequential module vcc 1.5 v 0.29 w/mhz pac7 contribution of a versatile used as a combinatorial module vcc 1.5 v 0.29 w/mhz pac8 average contribution of a routing net vcc 1.5 v 0.70 w/mhz pac9 contribution of an i/o input pin (standard dependent) vccxxxxiobx/vcc see ta b l e 2 - 9 and table 2-10 on page 2-11 pac10 contribution of an i/o output pin (standard dependent) vccxxxxiobx/vcc see ta b l e 2 - 11 and table 2-12 on page 2-11 pac11 average contribution of a ram block during a read operation vcc 1.5 v 25.00 w/mhz pac12 average contribution of a ram block during a write operation vcc 1.5 v 30.00 w/mhz pac13 dynamic contribution for pll vcc 1.5 v 2.60 w/mhz pac15 contribution of nvm block during a read operation (f < 33mhz) vcc 1.5 v 358.00 w/mhz pac16 1st contribution of nvm block during a read operation (f > 33mhz) vcc 1.5 v 12.88 mw pac17 2nd contribution of nvm block during a read operation (f > 33mhz) vcc 1.5 v 4.80 w/mhz pac18 main crystal oscillator cont ribution vccmainxtal 3.3 v 1.98 mw pac19a rc oscillator contribution vccrcosc 3.3 v 3.30 mw pac19b rc oscillator contribution vcc 1.5 v 3.00 mw pac20a analog block dynamic power contribution of the adc vcc33adcx 3.3 v 8.25 mw pac20b analog block dynamic power contribution of the adc vcc15adcx 1.5 v 3.00 mw pac21 low power crystal oscillator contribution vcclpxtal 3.3 v 33.00 w pac22 mss dynamic power contribution ? running drysthone at 100mhz 1 vcc 1.5 v 67.50 mw pac23 temperature monitor power contribution see table 2-92 on page 2-76 ?1.23mw pac24 current monitor power contribution see table 2-91 on page 2-75 ?1.03mw
actel smartfusion intelligent mixed signal fpgas revision 5 2-13 pac25 abps power contribution see table 2-94 on page 2-79 ?0.70mw pac26 sigma-delta dac power contribution 2 see table 2-96 on page 2-82 ?0.58mw pac27 comparator power contribution see table 2-95 on page 2-81 ?0.96mw pac28 voltage regulator power contribution 3 see table 2-97 on page 2-84 ? 36.30 mw notes: 1. for a different use of mss peripherals and resources, refer to smartpower. 2. assumes input = half scale operation mode. 3. assumes 100 ma load on 1.5 v domain. table 2-14 ? different components contributing to the static power consumption in smartfusion devices parameter definition power supply device units name domain a2f500 a2f200 pdc1 core static power contribution vcc 1.5 v 4.5 1.50 mw pdc2 device static power contribution in standby mode see table 2-8 on page 2-10 ?4.51.50mw pdc3 device static power contribution in time keeping mode see table 2-8 on page 2-10 3.3 v 0.00 mw pdc4 envm static power contribution see table 2-8 on page 2-10 1.5 v 1.19 mw pdc7 static contribution per input pin (standard dependent contribution) vccxxxxiobx/vcc see ta b l e 2 - 9 and table 2-10 on page 2-11 . pdc8 static contribution per input pin (standard dependent contribution) vccxxxxiobx/vcc see ta b l e 2 - 11 and table 2-12 on page 2-11 . pdc9 static contribution per pll vcc 1.5 v 2.55 mw table 2-15 ? envm dynamic power consumption parameter description condition min. typ. max. units envm system envm array operating power idle 795 a read operation see table 2-13 on page 2-12 . erase 900 a write 900 a pnvmctrl envm controller operating power 20 w/mhz table 2-13 ? different components contributing to dynamic power consumption in smartfusion devices parameter definition power supply device units name domain a2f500 a2f200
smartfusion dc and switching characteristics 2-14 revision 5 power calculation methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in the libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls/cccs as well as the nu mber and the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? the number of envm bl ocks used in the design ? the analog block used in the de sign, including the temperature monitor, current monitor, abps, sigma-delta dac, comparator, low power crystal oscillator, rc oscillator and the main crystal oscillator ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-16 on page 2-18 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-17 on page 2-18 . ? read rate and write rate to the memory?guidel ines are provided for typical applications in table 2-17 on page 2-18 . ? read rate to the envm blocks the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total soc mode, standby mode, and time keeping mode. p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat soc mode p stat = p dc1 + (n envm-blocks * p dc4 ) + (n inputs * p dc7 ) + (n outputs * p dc8 ) + (n plls * p dc9 ) n envm-blocks is the number of envm blocks available in the device. n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. n plls is the number of plls available in the device. standby mode p stat = p dc2 time keeping mode p stat = p dc3 total dynamic power consumption?p dyn soc mode p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll + p envm + p xtl-osc + p rc-osc + p ab + p lpxtal-osc + p mss
actel smartfusion intelligent mixed signal fpgas revision 5 2-15 standby mode p dyn = p rc-osc + p lpxtal-osc time keeping mode p dyn = p lpxtal-osc global clock dynamic contribution?p clock soc mode p clock = (p ac1 + n spine * p ac2 + n row * pac3 + n s-cell * p ac4 ) * f clk n spine is the number of global spines used in the user design?guideli nes are provided in table 2-16 on page 2-18 . n row is the number of versatile rows used in the design?guidelines are provided in table 2-16 on page 2-18 . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. standby mode and time keeping mode p clock = 0 w sequential cells dynamic contribution?p s-cell soc mode p s-cell = n s-cell * (p ac5 + ( 1 / 2) * p ac6 ) * f clk n s-cell is the number of versatiles used as sequent ial modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-16 on page 2-18 . f clk is the global clock signal frequency. standby mode and time keeping mode p s-cell = 0 w combinatorial cells dynamic contribution?p c-cell soc mode p c-cell = n c-cell * ( 1 / 2) * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-16 on page 2-18 . f clk is the global clock signal frequency. standby mode and time keeping mode p c-cell = 0 w routing net dynamic contribution?p net soc mode p net = (n s-cell + n c-cell ) * ( 1 / 2) * p ac8 * f clk n s-cell is the number versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-16 on page 2-18 . f clk is the frequency of the clock driving the logic including these nets.
smartfusion dc and switching characteristics 2-16 revision 5 standby mode and time keeping mode p net = 0 w i/o input buffer dynamic contribution?p inputs soc mode p inputs = n inputs * ( 2 / 2) * p ac9 * f clk where: n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-16 on page 2-18 . f clk is the global clock signal frequency. standby mode and time keeping mode p inputs = 0 w i/o output buffer dynamic contribution?p outputs soc mode p outputs = n outputs * ( 2 / 2) * 1 * p ac10 * f clk where: n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-16 on page 2-18 . 1 is the i/o buffer enable rate?guidelines are provided in table 2-17 on page 2-18 . f clk is the global clock signal frequency. standby mode and time keeping mode p outputs = 0 w fpga fabric sram dynamic contribution?p memory soc mode p memory = (n blocks * p ac11 * 2 * f read-clock ) + (n blocks * p ac12 * 3 * f write-clock ) where: n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. 2 is the ram enable rate for read op erations?guidelines are provided in table 2-17 on page 2-18 . 3 the ram enable rate for write operations?guidelines are provided in table 2-17 on page 2-18 . f write-clock is the memory write clock frequency. standby mode and time keeping mode p memory = 0 w pll/ccc dynamic contribution?p pll soc mode p pll = p ac13 * f clkout f clkin is the input clock frequency. f clkout is the output clock frequency. 1 standby mode and time keeping mode 1.the pll dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the pll, and the frequency of each output clock. if a pll is used to generate more than one output clock, include each output clock in the formula output clock by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution.
actel smartfusion intelligent mixed signal fpgas revision 5 2-17 p pll = 0 w embedded nonvolatile memory dynamic contribution?p envm soc mode the envm dynamic power consumption is a piecewise linear function of frequency. p envm = n envm-blocks * 4 * p ac15 * f read-envm when f read-envm 33 mhz, p envm = n envm-blocks * 4 *(p ac16 + p ac17 * f read-envm ) when f read-envm > 33 mhz where: n envm-blocks is the number of envm blocks used in the design. 4 is the envm enable rate for read operations. default is 0 (envm mainly in idle state). f read-envm is the envm read clock frequency. standby mode and time keeping mode p envm = 0 w main crystal oscillator dynamic contribution?p xtl-osc soc mode p xtl-osc = p ac18 standby mode p xtl-osc = 0 w time keeping mode p xtl-osc = 0 w low power oscillator crystal dynamic contribution?p lpxtal-osc operating, standby, and time keeping mode p lpxtal-osc = p ac21 rc oscillator dynamic contribution?p rc-osc soc mode p rc-osc = p ac19a + p ac19b standby mode and time keeping mode p rc-osc = 0 w analog system dynamic contribution?p ab soc mode p ab = p ac23 * n tm + p ac24 * n cm + p ac25 * n abps + p ac26 * n sdd + p ac27 * n comp + p adc * n adc + p vr where: n cm is the number of current monitor blocks n tm is the number of temperature monitor blocks n sdd is the number of sigma-delta dac blocks n abps is the number of abps blocks n adc is the number of adc blocks n comp is the number of comparator blocks p vr = p ac28 p adc = p ac20a + p ac20b
smartfusion dc and switching characteristics 2-18 revision 5 microcontroller subsystem dynamic contribution?p mss soc mode p mss = p ac22 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this m eans that the net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% , as all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8. enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when non-tristate output buffers are us ed, the enable rate should be 100%. table 2-16 ? toggle rate guidelines reco mmended for power calculation component defini tion guideline 1 toggle rate of versatile outputs 10% 2 i/o buffer toggle rate 10% table 2-17 ? enable rate guidelines recomme nded for power calculation component defini tion guideline 1 i/o output buffer enable rate toggle rate of the logic driving the output buffer 2 fpga fabric sram enable rate for read operations 12.5% 3 fpga fabric sram enable rate for write operations 12.5% 4 envm enable rate for read operations < 5%
actel smartfusion intelligent mixed signal fpgas revision 5 2-19 user i/o characteristics timing model figure 2-2 ? timing model operating conditions: ?1 speed, commercial temperature range (t j = 85c), worst case vcc = 1.425 v dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvpecl (applicable to advanced i/o banks only) lvpecl (applicable to advanced i/o banks only) lvds, blvds, m-lvds (applicable for advanced i/o banks only) lvttl 3.3 v output drive strength = 12 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 0.57 ns t pd = 0.49 ns t dp = 1.38 ns t pd = 0.89 ns t dp = 2.71 ns (advanced i/o banks) t pd = 0.51 ns t dp = 3.76 ns (advanced i/o banks) t pd = 0.48 ns t dp = 4.08 ns (advanced i/o banks) t pd = 0.47 ns t py = 0.78 ns (advanced i/o banks) t clkq = 0.56 ns t oclkq = 0.60 ns t sud = 0.44 ns t osud = 0.32 ns t dp = 2.71 ns (advanced i/o banks) t py = 0.78 ns (advanced i/o banks) t py = 1.27 ns t clkq = 0.56 ns t sud = 0.44 ns t py = 0.78 ns (advanced i/o banks) t iclkq = 0.24 ns t isud = 0.27 ns t py = 1.08 ns
smartfusion dc and switching characteristics 2-20 revision 5 figure 2-3 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50% 50% vih vcc vil t dout (r) din gnd t dout (f) 50% 50% vcc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
actel smartfusion intelligent mixed signal fpgas revision 5 2-21 figure 2-4 ? output buffer model and delays (example) t dp (r) pad vol t dp (f) v trip v trip voh vcc d 50% 50% vcc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
smartfusion dc and switching characteristics 2-22 revision 5 figure 2-5 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% vccxxxxiobx t zl v trip 50% t hz 90% vccxxxxiobx t zh v trip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls v trip 50% t zhs v trip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% vcc vcc vcc vccxxxxiobx vcc vcc vcc voh vol vol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
actel smartfusion intelligent mixed signal fpgas revision 5 2-23 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-18 ? summary of maximum and minimum dc input and output levels applicable to commercial conditions?software default settings applicable to fpga i/o banks i/o standard drive strgth. slew rate vil vih vol voh i ol 1 i oh 1 min. v max. v min. v max. v max. v min. vmama 3.3vlvttl/ 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * vccxxxxiobx 0.65* vccxxxxiobx 3.6 0.45 vccxxxxiobx ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.35 * vccxxxxiobx 0.65* vccxxxxiobx 3.6 0.25 * vccxxxxiobx 0.75* vccxxxxiobx 12 12 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications notes: 1. currents are measured at 85c junction temperature. 2. output slew rate can be extracted by the ibis models. table 2-19 ? summary of maximum and minimum dc input and output levels applicable to commercial conditions?software default settings applicable to mss i/o banks i/o standard drive strgth. slew rate vil vih vol voh i ol 1 i oh 1 min. v max. v min. v max. v max. v min. vmama 3.3vlvttl/ 3.3 v lvcmos 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 2.5 v lvcmos 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma high ?0.3 0.35* vccxxxxiobx 0.65* vccxxxxiobx 3.6 0.45 vccxxxxiobx ? 0.45 44 1.5 v lvcmos 2 ma high ?0.3 0.35* vccxxxxiobx 0.65* vccxxxxiobx 3.6 0.25* vccxxxxiobx 0.75* vccxxxxiobx 22 notes: 1. currents are measured at 85c junction temperature. 2. output slew rate can be extracted by the ibis models.
smartfusion dc and switching characteristics 2-24 revision 5 summary of i/o timing characte ristics ? default i/o software settings table 2-20 ? summary of maximum and minimum dc input levels applicable to commercial condit ions in all i/o bank types dc i/o standards commercial i il i ih a a 3.3 v lvttl / 3.3 v lvcmos 15 15 2.5 v lvcmos 15 15 1.8 v lvcmos 15 15 1.5 v lvcmos 15 15 3.3 v pci 15 15 3.3 v pci-x 15 15 table 2-21 ? summary of ac measuring points applicable to all i/o bank types standard measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 3.3 v pci 0.285 * vccxxxxiobx (rr) 0.615 * vccxxxxiobx (ff) 3.3 v pci-x 0.285 * vccxxxxiobx (rr) 0.615 * vccxxxxiobx (ff) lvds cross point lvpecl cross point table 2-22 ? i/o ac parameter definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer delay through the i/o interface t eout enable to output buffer tristate control delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
actel smartfusion intelligent mixed signal fpgas revision 5 2-25 table 2-23 ? summary of i/o timing character istics?software default settings ?1 speed grade, worst commercial-case conditions: t j = 85c, worst case vcc = 1.425 v, worst-case vccxxxxiobx (per standard) applicable to fpga i/o banks i/o standard drive strength slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3vlvttl/ 3.3 v lvcmos 12 ma high 35 ? 0.50 2.71 0.03 0. 78 0.32 2.76 2.17 2.46 2.75 4.48 3.88 ns 2.5 v lvcmos 12 ma high 35 ? 0.50 2. 73 0.03 1.01 0.32 2.78 2.63 2.53 2.64 4.50 4.35 ns 1.8 v lvcmos 12 ma high 35 ? 0.50 2.71 0.03 0.93 0.32 2.76 2.33 2.84 3.13 4.48 4.05 ns 1.5 v lvcmos 12 ma high 35 ? 0.50 3.13 0.03 1.10 0.32 3.19 2.74 3.03 3.22 4.90 4.46 ns 3.3 v pci per pci spec high 10 25 1 0.50 2.06 0.03 0.66 0.32 2.09 1.50 2.46 2.75 3.81 3.21 ns 3.3 v pci-x per pci-x spec high 10 25 1 0.50 2.06 0.03 0.64 0.32 2.09 1.50 2.46 2.75 3.81 3.21 ns lvds 24 ma high ? ? 0.50 1.44 0.03 1.27 ? ? ? ? ? ? ? ns lvpecl 24 ma high ? ? 0.50 1.38 0.03 1.08 ? ? ? ? ? ? ? ns notes: 1. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-10 on page 2-39 for connectivity. this resistor is not required during normal operation. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-24 ? summary of i/o timing character istics?software default settings ?1 speed grade, worst commercial-case conditions: t j = 85c, worst case vcc = 1.425 v, worst-case vccxxxxiobx (per standard) applicable to mss i/o banks i/o standard drive strength slew rate capacitive load (pf) external resistor t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) units 3.3 v lvttl / 3.3 v lvcmos 8 ma high 10 ? 0.18 3.34 0.07 0. 78 1.09 0.18 1.96 1.55 1.83 2.04 ns 2.5 v lvcmos 8 ma high 10 ? 0.18 3. 62 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns 1.8 v lvcmos 4 ma high 10 ? 0.18 4. 82 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns 1.5 v lvcmos 2 ma high 10 ? 0.18 2. 70 0.07 1.07 1.55 0.18 4.80 5.80 1.87 1.85 ns notes: 1. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-10 on page 2-39 for connectivity. this resistor is not required during normal operation. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-26 revision 5 detailed i/o dc characteristics table 2-25 ? input capacitance symbol definition cond itions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 2-26 ? i/o output buffer maximum resistances 1 applicable to fpga i/o banks standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3 v pci/pci-x per pci/pci-x specification 25 75 notes: 1. these maximum values are provided for information only. minimum output buffer resistance values depend on vccxxxxiobx, drive str ength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the microsemi soc products group website at http://www.actel.com/download/ibis/default.aspx (also generated by the soc products group libero ide toolset). 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec
actel smartfusion intelligent mixed signal fpgas revision 5 2-27 table 2-27 ? i/o output buffer maximum resistances 1 applicable to mss i/o banks standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 8ma 50 150 2.5 v lvcmos 8 ma 50 100 1.8 v lvcmos 4 ma 100 112 1.5 v lvcmos 2 ma 200 224 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on vccxxxxiobx, driv e strength selection, temperature, and proce ss. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the soc products group website at http://www.actel.com/download/ibis/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec table 2-28 ? i/o weak pull-up/pull-down resistances minimum and maximum weak pull-u p/pull-down resistance values vccxxxxiobx r (weak pull-up) 1 ( ) r (weak pull-down) 2 ( ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-down-max) = (v olspec ) / i (weak pull-down-min) 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i (weak pull-up-min)
smartfusion dc and switching characteristics 2-28 revision 5 table 2-29 ? i/o short currents i osh /i osl applicable to fpga i/o banks drive strength i osl (ma) * i osh (ma) * 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 127 132 24 ma 181 268 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 12 ma 74 65 16 ma 87 83 24 ma 124 169 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 51 45 12 ma 74 91 16 ma 74 91 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 6 ma 39 32 8 ma 55 66 12 ma 55 66 3.3 v pci/pci-x per pci/pci-x specification 109 103 note: *t j = 85c. table 2-30 ? i/o short currents i osh /i osl applicable to mss i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 8 ma 54 51 2.5 v lvcmos 8 ma 37 32 1.8 v lvcmos 4 ma 22 17 1.5 v lvcmos 2 ma 16 13 note: *t j = 85c
actel smartfusion intelligent mixed signal fpgas revision 5 2-29 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, which is the worst case for this type of analysis. for example, at 100c, the short current conditi on would have to be sustained for more than 2200 operation hours to cause a reliability concern. th e i/o design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-31 ? duration of short circ uit event before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months table 2-32 ? schmitt trigger input hysteresis hysteresis voltage value (typical) for schmitt mode input buffers input buffer configuration hysteresis value (typical) 3.3 v lvttl / lvcmos / pci / pci-x (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmitt trigger mode) 80 mv 1.5 v lvcmos (schmitt trigger mode) 60 mv table 2-33 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos no requirement 10 ns * 20 years (100c) lvds/b-lvds/ m-lvds/lvpec l no requirement 10 ns * 10 years (100c) * the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible t he input signal is to the board noise. microsemi soc products group recommends signal integrity evaluatio n/characterization of the system to ensure that there is no excessive noise coupling into input signals.
smartfusion dc and switching characteristics 2-30 revision 5 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-34 ? minimum and maximum dc input and output levels applicable to fpga i/o banks 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 15 15 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 15 15 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 15 15 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 15 15 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 15 15 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-35 ? minimum and maximum dc input and output levels applicable to mss i/o banks 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15 notes: 1. currents are measured at 100c junction temperature and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-6 ? ac loading table 2-36 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 0 3.3 1.4 ? 35 note: *measuring point = v trip. see table 2-21 on page 2-24 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to gnd for t hz / t zh / t zhs r to vccxxxxiobx for t lz / t zl / t zls 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
actel smartfusion intelligent mixed signal fpgas revision 5 2-31 timing characteristics table 2-37 ? 3.3 v lvttl / 3.3 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 3.0 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 7.05 0.04 0.94 0.39 7.18 6.06 2.44 2. 41 9.24 8.12 ns ?1 0.50 5.87 0.03 0.78 0.32 5. 98 5.05 2.03 2.00 7.70 6.77 ns 8 ma std. 0.60 4.52 0.04 0.94 0.39 4.60 3.75 2.75 2. 95 6.66 5.80 ns ?1 0.50 3.76 0.03 0.78 0.32 3. 83 3.12 2.29 2.46 5.55 4.84 ns 12 ma std. 0.60 3.25 0.04 0.94 0.39 3.31 2.60 2.96 3.30 5.37 4.66 ns ?1 0.50 2.71 0.03 0.78 0.32 2.76 2.17 2.46 2.75 4.48 3.88 ns 16 ma std. 0.60 3.07 0.04 0.94 0.39 3.12 2.36 3.00 3. 39 5.18 4.42 ns ?1 0.50 2.56 0.03 0.78 0.32 2. 60 1.97 2.50 2.82 4.32 3.68 ns 24 ma std. 0.60 2.83 0.04 0.94 0.39 2.88 1.95 3.06 3. 74 4.94 4.01 ns ?1 0.50 2.36 0.03 0.78 0.32 2. 40 1.63 2.55 3.11 4.12 3.34 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-38 ? 3.3 v lvttl / 3.3 v lvcmos low slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 3.0 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 9.44 0.04 0.94 0.39 9.62 8.19 2.43 2.26 11.67 10.25 ns ?1 0.50 7.87 0.03 0.78 0.32 8. 01 6.83 2.03 1.88 9.73 8.54 ns 8 ma std. 0.60 6.70 0.04 0.94 0.39 6.82 5.78 2.74 2.80 8.88 7.84 ns ?1 0.50 5.58 0.03 0.78 0.32 5. 68 4.82 2.29 2.33 7.40 6.54 ns 12 ma std. 0.60 5.14 0.04 0.94 0.39 5.23 4.48 2.95 3.14 7.29 6.54 ns ?1 0.50 4.28 0.03 0.78 0.32 4. 36 3.74 2.46 2.62 6.08 5.45 ns 16 ma std. 0.60 4.79 0.04 0.94 0.39 4.88 4.20 3.00 3.23 6.94 6.26 ns ?1 0.50 3.99 0.03 0.78 0.32 4. 07 3.50 2.50 2.69 5.78 5.22 ns 24 ma std. 0.60 4.46 0.04 0.94 0.39 4.55 4.18 3.05 3.57 6.61 6.24 ns ?1 0.50 3.72 0.03 0.78 0.32 3. 79 3.49 2.54 2.98 5.50 5.20 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-39 ? 3.3 v lvttl / 3.3 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 3.0 v applicable to mss i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 8 ma std. 0.22 4.01 0.09 0.94 1.30 0.22 2.35 1.86 2.20 2.45 ns ?1 0.18 3.34 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-32 revision 5 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. it uses a 5 v?toler ant input buffer and push-pull output buffer. table 2-40 ? minimum and maximum dc input and output levels applicable to fpga i/o banks 2.5 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 15 15 4 ma ?0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 15 15 6 ma ?0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 15 15 8 ma ?0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 15 15 12 ma ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 15 15 16 ma ?0.3 0.7 1.7 2.7 0.7 1.7 16 16 87 83 15 15 24 ma ?0.3 0.7 1.7 2.7 0.7 1.7 24 24 124 169 15 15 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-41 ? minimum and maximum dc input and output levels applicable to mss i/o banks 2.5 v lvcmos vil v ih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max., ma 1 a 2 a 2 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 15 15 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-42 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 0 2.5 1.2 ? 35 * measuring point = v trip. see table 2-21 on page 2-24 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to gnd for t hz / t zh / t zhs r to vccxxxxiobx for t lz / t zl / t zls 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
actel smartfusion intelligent mixed signal fpgas revision 5 2-33 timing characteristics table 2-43 ? 2.5 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 2.3 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 7.97 0.04 1.21 0.39 7.21 7.97 2.46 2.12 9.27 10.03 ns ?1 0.50 6.65 0.03 1.01 0.32 6. 01 6.65 2.05 1.77 7.72 8.36 ns 8 ma std. 0.60 4.76 0.04 1.21 0.39 4.64 4.76 2.81 2.76 6.69 6.81 ns ?1 0.50 3.96 0.03 1.01 0.32 3. 86 3.96 2.34 2.30 5.58 5.68 ns 12 ma std. 0.60 3.28 0.04 1.21 0.39 3.34 3.16 3.04 3.16 5.40 5.22 ns ?1 0.50 2.73 0.03 1.01 0.32 2.78 2.63 2.53 2.64 4.50 4.35 ns 16 ma std. 0.60 3.09 0.04 1.21 0.39 3.14 2.82 3.09 3.27 5.20 4.88 ns ?1 0.50 2.57 0.03 1.01 0.32 2. 62 2.35 2.58 2.72 4.33 4.06 ns 24 ma std. 0.60 2.84 0.04 1.21 0.39 2.90 2.25 3.16 3.68 4.95 4.31 ns ?1 0.50 2.37 0.03 1.01 0.32 2. 41 1.87 2.64 3.07 4.13 3.59 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-44 ? 2.5 v lvcmos low slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 2.3 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 10.49 0.04 1.21 0.39 10.33 10.49 2.46 2.03 12.38 12.55 ns ?1 0.50 8.74 0.03 1.01 0.32 8.61 8.74 2.05 1.69 10.32 10.46 ns 8 ma std. 0.60 7.33 0.04 1.21 0.39 7.46 7.19 2.81 2.66 9.52 9.25 ns ?1 0.50 6.11 0.03 1.01 0.32 6.22 5.99 2.34 2.22 7.93 7.71 ns 12 ma std. 0.60 5.69 0.04 1.21 0.39 5.79 5.45 3.04 3.06 7.85 7.51 ns ?1 0.50 4.74 0.03 1.01 0.32 4.83 4.54 2.53 2.55 6.54 6.26 ns 16 ma std. 0.60 5.31 0.04 1.21 0.39 5.40 5.09 3.09 3.16 7.46 7.14 ns ?1 0.50 4.42 0.03 1.01 0.32 4.50 4.24 2.58 2.64 6.22 5.95 ns 24 ma std. 0.60 5.07 0.04 1.21 0.39 5.07 5.07 3.16 3.56 7.12 7.13 ns ?1 0.50 4.22 0.03 1.01 0.32 4.22 4.22 2.63 2.97 5.94 5.94 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-45 ? 2.5 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 3.0 v applicable to mss i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 8 ma std. 0.22 4.34 0.09 1.18 1.39 0.22 2.40 2.18 2.19 2.32 ns ?1 0.18 3.62 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-34 revision 5 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standa rd (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-46 ? minimum and maximum dc input and output levels applicable to fpga i/o banks 1.8 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.9 0.45 vccxxxxiobx ? 0.45 2 2 11 9 15 15 4 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.9 0.45 vccxxxxiobx ? 0.45 4 4 22 17 15 15 6 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.9 0.45 vccxxxxiobx ? 0.45 6 6 44 35 15 15 8 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.9 0.45 vccxxxxiobx ? 0.45 8 8 51 45 15 15 12 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.9 0.45 vccxxxxiobx ? 0.45 12 12 74 91 15 15 16 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.9 0.45 vccxxxxiobx ? 0.45 16 16 74 91 15 15 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-47 ? minimum and maximum dc input and output levels applicable to mss i/o banks 1.8 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 4 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 3.6 0.45 vccxxxxiobx ? 0.45 4 4 22 17 15 15 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-48 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 0 1.8 0.9 ? 35 * measuring point = v trip. see table 2-21 on page 2-24 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to gnd for t hz / t zh / t zhs r to vccxxxxiobx for t lz / t zl / t zls 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
actel smartfusion intelligent mixed signal fpgas revision 5 2-35 timing characteristics table 2-49 ? 1.8 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 1.7 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.60 10.92 0.04 1.12 0.3 9 8.41 10.92 2.55 1.52 10.47 12.98 ns ?1 0.50 9.10 0.03 0.93 0.32 7.01 9.10 2.13 1.27 8.72 10.82 ns 4 ma std. 0.60 6.27 0.04 1.12 0. 39 5.40 6.37 2.97 2.61 7.45 8.42 ns ?1 0.50 5.30 0.03 0.93 0.32 4.50 5.30 2.47 2.18 6.21 7.02 ns 6 ma std. 0.60 4.09 0.04 1.12 0.39 3.85 4.09 3.25 3.11 5.91 6.15 ns ?1 0.50 3.41 0.03 0.93 0.32 3.21 3.41 2.71 2.59 4.92 5.13 ns 8 ma std. 0.60 3.61 0.04 1.12 0.39 3.62 3.61 3.31 3.24 5.67 5.67 ns ?1 0.50 3.01 0.03 0.93 0.32 3.01 3.01 2.76 2.70 4.73 4.73 ns 12 ma std. 0.60 3.25 0.04 1.12 0.39 3.31 2.80 3.41 3.76 5.37 4.86 ns ?1 0.50 2.71 0.03 0.93 0.32 2.76 2.33 2.84 3.13 4.48 4.05 ns 16 ma std. 0.60 3.25 0.04 1.12 0.39 3.31 2.80 3.41 3.76 5.37 4.86 ns ?1 0.50 2.71 0.03 0.93 0.32 2.76 2.33 2.84 3.13 4.48 4.05 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-50 ? 1.8 v lvcmos low slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 1.7 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.60 14.30 0.04 1.12 0.39 12.99 14.30 2.56 1.47 15.05 16.35 ns ?1 0.50 11.91 0.03 093 0.32 10.83 11.91 2.13 1.23 12.54 13.63 ns 4 ma std. 0.60 9.64 0.04 1.12 0.39 9.58 9.64 2.97 2.52 11.64 11.70 ns ?1 0.50 8.04 0.03 0.93 0.32 7.99 8.04 2.48 2.10 9.70 9.75 ns 6 ma std. 0.60 7.41 0.04 1.12 0.39 7.55 7.22 3.25 3.01 9.61 9.28 ns ?1 0.50 6.17 0.03 0.93 0.32 6.29 6.02 2.71 2.51 8.00 7.73 ns 8 ma std. 0.60 6.91 0.04 1.12 0.39 7.03 6.72 3.32 3.14 9.09 8.78 ns ?1 0.50 5.76 0.03 0.93 0.32 5.86 5.60 2.77 2.62 7.58 7.31 ns 12 ma std. 0.60 6.71 0.04 1.12 0.39 6.66 6.71 3.41 3.64 8.72 8.77 ns ?1 0.50 5.59 0.03 0.93 0.32 5.55 5.59 2.84 3.03 7.27 7.31 ns 16 ma std. 0.60 6.71 0.04 1.12 0.39 6.66 6.71 3.41 3.64 8.72 8.77 ns ?1 0.50 5.59 0.03 0.93 0.32 5.55 5.59 2.84 3.03 7.27 7.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-36 revision 5 table 2-51 ? 1.8 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 1.7 v applicable to mss i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std. 0.22 5.78 0.09 1.09 1.64 0.22 2.82 2.72 2.21 2.25 ns ?1 0.18 4.82 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-37 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-52 ? minimum and maximum dc input and output levels applicable to fpga i/o banks 1.5 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.575 0.25* vccxxxxiobx 0.75 * vccxxxxiobx 2 2 16 13 15 15 4 ma ? 0.3 0.35* vccxxxxiobx 0.65 * vccxxxxiobx 1.575 0.25* vccxxxxiobx 0.75 * vccxxxxiobx 4 4 33 25 15 15 6 ma ? 0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.575 0.25* vccxxxxiobx 0.75 * vccxxxxiobx 6 6 39 32 15 15 8 ma ? 0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.575 0.25* vcc 0.75 * vccxxxxiobx 8 8 55 66 15 15 12 ma ? 0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.575 0.25 * vccxxxxiobx 0.75 * vccxxxxiobx 12 12 55 66 15 15 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-53 ? minimum and maximum dc input and output levels applicable to mss i/o banks 1.5 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vccxxxxiobx 0.65 * vccxxxxiobx 1.575 0.25 * vccxxxxiobx 0.75 * vccxxxxiobx 2 2 16 13 15 15 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-54 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 0 1.5 0.75 ? 35 * measuring point = v trip. see table 2-21 on page 2-24 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to gnd for t hz / t zh / t zhs r to vccxxxxiobx for t lz / t zl / t zls 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
smartfusion dc and switching characteristics 2-38 revision 5 timing characteristics table 2-55 ? 1.5 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 1.425 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 m std. 0.60 7.70 0.04 1.32 0.39 6.28 7.70 3.12 2.55 8.34 9.76 ns ?1 0.50 6.42 0.03 1.10 0.32 5.23 6.42 2.60 2.12 6.95 8.13 ns 4 ma std. 0.60 4.89 0.04 1.32 0. 39 4.46 4.89 3.44 3.13 6.52 6.95 ns ?1 0.50 4.08 0.03 1.10 0.32 3.72 4.08 2.87 2.61 5.44 5.79 ns 6 ma std. 0.60 4.30 0.04 1.32 0.39 4.19 4.30 3.52 3.28 6.24 6.35 ns ?1 0.50 3.58 0.03 1.10 0.32 3.49 3.58 2.93 2.73 5.20 5.30 ns 8 ma std. 0.60 3.75 0.04 1.32 0.39 3.82 3.29 3.63 3.87 5.88 5.35 ns ?1 0.50 3.13 0.03 1.10 0.32 3.19 2.74 3.03 3.22 4.90 4.46 ns 12 ma std. 0.60 3.75 0.04 1.32 0.39 3.82 3.29 3.63 3.87 5.88 5.35 ns ?1 0.50 3.13 0.03 1.10 0.32 3.19 2.74 3.03 3.22 4.90 4.46 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-56 ? 1.5 v lvcmos low slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 1.4 v applicable to fpga i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.60 11.77 0.04 1.32 0.39 11.79 11.77 3.13 2.43 13.85 13.83 ns ?1 0.50 9.81 0.03 1.10 0.32 9.83 9.81 2.61 2.03 11.54 11.52 ns 4 ma std. 0.60 9.21 0.04 1.32 0.39 9.38 8.79 3.45 3.01 11.44 10.85 ns ?1 0.50 7.68 0.03 1.10 0.32 7.82 7.32 2.88 2.51 9.54 9.04 ns 6 ma std. 0.60 8.59 0.04 1.32 0.39 8.75 8.18 3.53 3.16 10.81 10.24 ns ?1 0.50 7.16 0.03 1.10 0.32 7.29 6.82 2.94 2.63 9.01 8.54 ns 8 ma std. 0.60 8.20 0.04 1.32 0.39 8.35 8.19 3.64 3.73 10.41 10.25 ns ?1 0.50 6.83 0.03 1.10 0.32 6.96 6.82 3.03 3.11 8.68 8.54 ns 12 ma std. 0.60 8.20 0.04 1.32 0.39 8.35 8.19 3.64 3.73 10.41 10.25 ns ?1 0.50 6.83 0.03 1.10 0.32 6.96 6.82 3.03 3.11 8.68 8.54 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-57 ? 1.5 v lvcmos high slew worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 3.0 v applicable to mss i/o banks drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.22 3.24 0.09 1.28 1.86 0.22 5.76 6.96 2.24 2.21 ns ?1 0.18 2.70 0.07 1.07 1.55 0.18 4.80 5.80 1.87 1.85 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-39 3.3 v pci, 3.3 v pci-x peripheral component interface for 3.3 v standard specifies support for 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pci/pci-x specific ations for the datapath; soc products group loadings for enable path characterization are described in figure 2-10 . ac loadings are defined per pci/pci- x specifications for the datapath; soc products group loading for tristate is described in table 2-59 . timing characteristics table 2-58 ? minimum and maximum dc input and output levels 3.3 v pci/pci-x vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 per pci specification per pci curves 15 15 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-10 ? ac loading test point enable path r to vccxxxxiobx for t lz / t zl / t zls 10 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz r to gnd for t hz / t zh / t zhs r = 1 k test point datapath r = 25 r to vccxxxxiobx for t dp (f) r to gnd for t dp (r) table 2-59 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 0 3.3 0.285 * vccxxxxiobx for t dp(r) 0.615 * vccxxxxiobx for t dp(f) ?10 * measuring point = v trip. see table 2-21 on page 2-24 for a complete table of trip points. table 2-60 ? 3.3 v pci worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 3.0 v applicable to fpga i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.60 2.47 0.04 0.80 0.39 2. 51 1.80 2.96 3.30 4.57 3.85 ns ?1 0.50 2.06 0.03 0.66 0.32 2.09 1.50 2.46 2.75 3.81 3.21 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-61 ? 3.3 v pci-x worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccxxxxiobx = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.60 2.47 0.04 0.77 0.39 2. 51 1.80 2.96 3.30 4.57 3.85 ns ?1 0.50 2.06 0.03 0.64 0.32 2.09 1.50 2.46 2.75 3.81 3.21 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-40 revision 5 differential i/o characteristics physical implementation configuration of the i/o modules as a differential pair is handled by soc products group designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjuncti on with the embedded input r egister (inreg), output register (outreg), enable register (enreg), an d double data rate (ddr). however, there is no support for bidirectional i/os or tristates with the lvpecl standards. lvds low-voltage differential signaling (ansi/tia/eia-644 ) is a high-speed, differential i/o standard. it requires that one data bit be carried through two si gnal lines, so two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitter and receiver is shown in an example in figure 2-11 . the building blocks of the lvds transmitter-receiver are one transmitte r macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvpecl implementation because the output standard specifications are different. along with lvds i/o, smartfusion also supports bus lvds structure and multipoint lvds (m-lvds) configuration (up to 40 nodes). figure 2-11 ? lvds circuit diag ram and board-level implementation 140 100 z 0 = 50 z 0 = 50 165 165 + ? p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12
actel smartfusion intelligent mixed signal fpgas revision 5 2-41 timing characteristics table 2-62 ? lvds minimum and maximum dc input and output levels dc parameter description min. typ. max. units vccfpgaiobx supply voltage 2.375 2.5 2.625 v vol output low voltage 0.9 1.075 1.25 v voh output high voltage 1.25 1.425 1.6 v i ol 1 output lower current 0.65 0.91 1.16 ma i oh 1 output high current 0.65 0.91 1.16 ma vi input voltage 0 2.925 v i ih 2 input high leakage current 15 a i il 2 input low leakage current 15 a v odiff differential output voltage 250 350 450 mv v ocm output common mode voltage 1.125 1.25 1.375 v v icm input common mode voltage 0.05 1.25 2.35 v v idiff input differential voltage 100 350 mv notes: 1. i ol /i oh defined by v odiff /(resistor network). 2. currents are measured at 85c junction temperature. table 2-63 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) 1.075 1.325 cross point ? * measuring point = v trip. see table 2-21 on page 2-24 for a complete tabl e of trip points. table 2-64 ? lvds worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccfpgaiobx = 2.3 v speed grade t dout t dp t din t py units std. 0.60 1.73 0.04 1.53 ns ?1 0.50 1.44 0.03 1.27 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-42 revision 5 b-lvds/m-lvds bus lvds (b-lvds) and multipoint lvds (m-lvds) s pecifications extend the existing lvds standard to high-performance multipoint bus applications. multid rop and multipoint bus configurations may contain any combination of drivers, receiv ers, and transceivers. soc products group lvds drivers provide the higher drive current required by b-lvds and m-lvds to accommodate the loading. the drivers require series terminations for better signal quality and to control voltage swing. termination is also required at both ends of the bus since the driver can be locate d anywhere on the bus. these configurations can be implemented using the tribuf_lvds and bibuf_lvds macros along with appr opriate terminations. multipoint designs using soc products group lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sample application is given in figure 2-12 . the input and output buffer delays are available in the lvds section in ta b l e 2 - 6 4 . example: for a bus consisting of 20 equidistant lo ads, the following terminations provide the required differential voltage, in worst-case commercial op erating conditions, at the farthest receiver: r s =60 and r t =70 , given z 0 =50 (2") and z stub =50 (~1.5"). figure 2-12 ? b-lvds/m-lvds multipoint application using lvds i/o buffers ... r t r t bibuf_lvds r + - t + - r + - t + - d + - en en en en en receiver transceiver receiver transceiver driver r s r s r s r s r s r s r s r s r s r s z stub z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0
actel smartfusion intelligent mixed signal fpgas revision 5 2-43 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differ ential i/o standard. it requires that one data bit be carried through two signal lines . like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitte r and receiver is shown in an example in figure 2-13 . the building blocks of the lvpecl transmitter-receiver are one transm itter macro, one rece iver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvds implementation beca use the output standard specifications are different. timing characteristics figure 2-13 ? lvpecl circuit diagram and board-level im plementation table 2-65 ? minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units vccfpgaiobx supply voltage 3.0 3.3 3.6 v vol output low voltage 0.9 6 1.27 1.06 1.43 1.30 1.57 v voh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v v il , v ih input low, input high voltages 0 3.3 0 3.6 0 3.9 v v odiff differential output voltage 0.625 0.97 0.625 0.97 0.625 0.97 v v ocm output common-mode voltage 1. 762 1.98 1.762 1.98 1.762 1.98 v v icm input common-mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v v idiff input differential voltage 300 300 300 mv table 2-66 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) 1.64 1.94 cross point ? * measuring point = v trip. see table 2-21 on page 2-24 for a complete table of trip points. 187 w 100 z 0 = 50 z 0 = 50 100 100 + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12 table 2-67 ? lvpecl worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v, worst-case vccfpgaiobx = 3.0 v speed grade t dout t dp t din t py units std. 0.60 1.66 0.04 1.29 ns ?1 0.50 1.38 0.03 1.08 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-44 revision 5 i/o register specifications fully registered i/o buffers with synchronous enable and asynchronous preset figure 2-14 ? timing model of registered i/o buffers with synchronous enable and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive-edge triggered data output register and enable output register with: active high enable active high preset postive-edge triggered pad out clk enable preset data_out data eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
actel smartfusion intelligent mixed signal fpgas revision 5 2-45 table 2-68 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of the output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the output enable register j, h t oesue enable setup time for the output enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time for the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of th e input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a * see figure 2-14 on page 2-44 for more information.
smartfusion dc and switching characteristics 2-46 revision 5 fully registered i/o buffers with synchronous enable and asynchronous clear figure 2-15 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear enable clk pad out clk enable clr data_out data y aa eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf data input i/o register with active high enable active high clear positive-edge triggered data output register and enable output register with active high enable active high clear positive-edge triggered
actel smartfusion intelligent mixed signal fpgas revision 5 2-47 table 2-69 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the output enable register kk, hh t oehe enable hold time for the output enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa * see figure 2-15 on page 2-46 for more information.
smartfusion dc and switching characteristics 2-48 revision 5 input register timing characteristics figure 2-16 ? input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-70 ? input data register propagation delays worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 std. units t iclkq clock-to-q of the input data register 0.24 0.29 ns t isud data setup time for the input data register 0.27 0.32 ns t ihd data hold time for the input data register 0.00 0.00 ns t isue enable setup time for the input data register 0.38 0.45 ns t ihe enable hold time for the input data register 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the i nput data register 0.46 0.55 ns t ipre2q asynchronous preset-to-q of the input data register 0.46 0.55 ns t iremclr asynchronous clear removal time for the input data register 0.00 0.00 ns t irecclr asynchronous clear recovery time fo r the input data register 0.23 0.27 ns t irempre asynchronous preset removal time for the input data register 0.00 0.00 ns t irecpre asynchronous preset recovery time fo r the input data register 0.23 0.27 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.22 0.22 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.22 0.22 ns t ickmpwh clock minimum pulse width high for the input data register 0.36 0.36 ns t ickmpwl clock minimum pulse width low for the input data register 0.32 0.32 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-49 output register timing characteristics figure 2-17 ? output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-71 ? output data register propagation delays worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 std. units t oclkq clock-to-q of the output data register 0.60 0.72 ns t osud data setup time for the outp ut data register 0.32 0.38 ns t ohd data hold time for the output data register 0.00 0.00 ns t osue enable setup time for the outp ut data register 0.44 0.53 ns t ohe enable hold time for the output data register 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 0.82 0.98 ns t opre2q asynchronous preset-to-q of the output data register 0.82 0.98 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.23 0.27 ns t orempre asynchronous preset removal time fo r the output data register 0.00 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.23 0.27 ns t owclr asynchronous clear minimum pulse width for the output data register 0.22 0.22 ns t owpre asynchronous preset minimum pulse width for the output data register 0.22 0.22 ns t ockmpwh clock minimum pulse width high for the output data register 0.36 0.36 ns t ockmpwl clock minimum pulse width low for the output data register 0.32 0.32 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-50 revision 5 output enable register timing characteristics figure 2-18 ? output enable register timing diagram 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-72 ? output enable register propagation delays worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 std. units t oeclkq clock-to-q of the output enable register 0.45 0.54 ns t oesud data setup time for the output enable register 0.32 0.38 ns t oehd data hold time for the output enable register 0.00 0.00 ns t oesue enable setup time for the output enable register 0.44 0.53 ns t oehe enable hold time for the output enable register 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the ou tput enable register 0.68 0.81 ns t oepre2q asynchronous preset-to-q of the output enable register 0.68 0.81 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.23 0.27 ns t oerempre asynchronous preset removal time for the output enable register 0.00 0.00 ns t oerecpre asynchronous preset recovery time fo r the output enable register 0.23 0.27 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.22 0.22 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.22 0.22 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.36 0.36 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.32 0.32 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-51 ddr module specifications input ddr module figure 2-19 ? input ddr timing model table 2-73 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
smartfusion dc and switching characteristics 2-52 revision 5 timing characteristics figure 2-20 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-74 ? input ddr propagation delays worst commercial-case conditions: t j = 85c, worst case vcc = 1.425 v parameter description ?1 units t ddriclkq1 clock-to-out out_qr for input ddr 0.39 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.28 ns t ddrisud data setup for input ddr 0.29 ns t ddrihd data hold for input ddr 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.58 ns t ddriclr2q2 asynchronous clear-to-out ou t_qf for input ddr 0.47 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.23 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.22 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.36 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.32 ns f ddrimax maximum frequency for input ddr 350 mhz note: for derating values at specific junction te mperature and voltage-supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-53 output ddr module figure 2-21 ? output ddr timing model table 2-75 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x a b d e c c b outbuf data_r (from core)
smartfusion dc and switching characteristics 2-54 revision 5 timing characteristics figure 2-22 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-76 ? output ddr propagation delays worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 units t ddroclkq clock-to-out of ddr for output ddr 0.71 ns t ddrosud1 data_f data setup for output ddr 0.38 ns t ddrosud2 data_r data setup for output ddr 0.38 ns t ddrohd1 data_f data hold for output ddr 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 0.81 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.23 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.22 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.36 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.32 ns f ddomax maximum frequency for the output ddr 350 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-55 versatile characteristics versatile specifications as a combinatorial module the smartfusion library offers all combinations of lu t-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the igloo/e, fusion, proasic3/e, and smartfusion macro library guide . figure 2-23 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
smartfusion dc and switching characteristics 2-56 revision 5 figure 2-24 ? timing model and waveforms t pd a b t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell y nand2 or any combinatorial logic t pd t pd 50% vcc vcc vcc 50% gnd a, b, c 50% 50% 50% (rr) (rf) gnd out out gnd 50% (ff) (fr) t pd t pd
actel smartfusion intelligent mixed signal fpgas revision 5 2-57 timing characteristics versatile specifications as a sequential module the smartfusion library offers a wid e variety of sequential cells, incl uding flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the library. for more details, refer to the igloo/e, fusion, proasic3/e, and smartfusion macro library guide . table 2-77 ? combinatorial cell propagation delays worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v combinatorial cell equation parameter ?1 std. units inv y = !a t pd 0.41 0.49 ns and2 y = a b t pd 0.48 0.57 ns nand2 y = !(a b) t pd 0.48 0.57 ns or2 y = a + b t pd 0.49 0.59 ns nor2 y = !(a + b) t pd 0.49 0.59 ns xor2 y = a bt pd 0.75 0.90 ns maj3 y = maj(a, b, c) t pd 0.71 0.85 ns xor3 y = a b ct pd 0.89 1.07 ns mux2 y = a !s + b s t pd 0.51 0.62 ns and3 y = a b c t pd 0.57 0.68 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. figure 2-25 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
smartfusion dc and switching characteristics 2-58 revision 5 timing characteristics figure 2-26 ? timing model and waveforms pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-78 ? register delays worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 std. units t clkq clock-to-q of the core register 0.56 0.67 ns t sud data setup time for the core register 0.44 0.52 ns t hd data hold time for the core register 0.00 0.00 ns t sue enable setup time for the core register 0.46 0.55 ns t he enable hold time for the core register 0.00 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.41 0.49 ns t pre2q asynchronous preset-to-q of the core register 0.41 0.49 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.23 0.27 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.23 0.27 ns t wclr asynchronous clear minimum pulse width for the core register 0.22 0.22 ns t wpre asynchronous preset minimum pulse width for the core register 0.22 0.22 ns t ckmpwh clock minimum pulse width high for the core register 0.32 0.32 ns t ckmpwl clock minimum pulse width low for the core register 0.36 0.36 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-59 global resource characteristics a2f200 clock tree topology clock delays are device-specific. figure 2-27 is an example of a global tree used for clock routing. the global tree presented in figure 2-27 is driven by a ccc located on the we st side of the a2f200 device. it is used to drive all d-flip-flops in the device. figure 2-27 ? example of global tree use in an a2f200 device for clock routing central global rib versatile rows global spine ccc
smartfusion dc and switching characteristics 2-60 revision 5 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-63 . ta b l e 2 - 8 0 presents minimum and maximum global clock delays for the a2f200 device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics table 2-79 ? a2f500 global resource worst commercial-case conditions: t j = 85c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.56 0.77 0.67 0.92 ns t rckh input high delay for global clock 0.56 0.81 0.67 0.97 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.25 0.30 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-80 ? a2f200 global resource worst commercial-case conditions: t j = 85c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.50 0.75 0.60 0.90 ns t rckh input high delay for global clock 0.50 0.79 0.60 0.95 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.29 0.35 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-61 rc oscillator the table below describes the electrical characteristics of the rc oscillator. rc oscillator ch aracteristics table 2-81 ? electrical characteristi cs of the rc oscillator parameter description condition min. typ. max. units frc operating frequency 100 mhz accuracy temperature: 0c to 85c voltage: 3.3 v 5% 1 % output jitter period jitter (at 5 k cycles) 100 ps cycle-to-cycle jitter (at 5 k cycles) 100 ps period jitter (at 5 k cycles) with 1 khz / 300 mv peak-to-peak noise on power supply 150 ps cycle-to-cycle jitter (a t 5 k cycles) with 1 khz / 300 mv peak-to-peak noise on power supply 150 ps output duty cycle 3.3 v domain 1 % idynrc operating current 1.5 v domain 2 ma
smartfusion dc and switching characteristics 2-62 revision 5 main and lower power crystal oscillator the tables below describes the electrical characteri stics of the main and low power crystal oscillator. table 2-82 ? electrical characteri stics of the main crystal oscillator parameter description conditio n min. typ. max. units operating frequency using external crystal 0.032 20 mhz using ceramic resonator 0.5 8 mhz using rc network 0.032 4 mhz output duty cycle 50 % output jitter with 10 mhz crystal 50 ps rms idynxtal operating current rc 0.6 ma 0.032?0.2 0.6 ma 0.2?2.0 0.6 ma 2.0?20.0 0.6 ma istbxtal standby current of crystal oscillator 10 a psrrxtal power supply noise tolerance 0.5 vp-p vihxtal input logic level high 90% of vcc v vilxtal input logic level low 10% of vcc v startup time rc s 0.032?0.2 s 0.2?2.0 s 2.0?20.0 s table 2-83 ? electrical characte ristics of the low power oscillator parameter description condition min. typ. max. units operating frequency 32 khz output duty cycle 50 % output jitter 50 ps rms idynxtal operating current 32 khz 10 a istbxtal standby current of crystal oscillator a psrrxtal power supply noise tolerance 0.5 vp-p vihxtal input logic level high 90% of vcc v vilxtal input logic level low 10% of vcc v startup time test load used: 20 pf 2.5 s
actel smartfusion intelligent mixed signal fpgas revision 5 2-63 clock conditioning circuits ccc electrical specifications timing characteristics table 2-84 ? smartfusion ccc/ pll specification parameter minimum typical maximum units clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 1 mhz delay increments in programmable delay blocks 2, 3 160 ps number of programmable values in each programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-peak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 0.50% 0.70% 24 mhz to 100 mhz 1.00% 1.20% 100 mhz to 250 mhz 1.75% 2.00% 250 mhz to 350 mhz 2.50% 5.60% acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 4 lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 5.15 % delay range in block: programmable delay 1 2,3 0.6 5.56 ns delay range in block: programmable delay 2 2,3 0.025 5.56 ns delay range in block: fixed delay 2,3 2.2 ns notes: 1. one of the ccc outputs (gla0) is used as an mss clock and is limited to 100 mhz (maximum) by software. details regarding ccc/pll are in the "plls, cl ock conditioning circ uitry, and on-chip crystal o scillators" ch apter of the smartfusion microcontroller subsystem user's guide . 2. this delay is a function of voltage and temperature. see table 2-7 on page 2-9 for deratings. 3. t j = 25c, vcc = 1.5 v 4. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to the pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter. note: peak-to-peak jitter meas urements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-28 ? peak-to-peak jitter definition t period_max t period_min output signal
smartfusion dc and switching characteristics 2-64 revision 5 fpga fabric sram and fifo characteristics fpga fabric sram figure 2-29 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
actel smartfusion intelligent mixed signal fpgas revision 5 2-65 timing waveforms figure 2-30 ? ram read for pass-through output figure 2-31 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
smartfusion dc and switching characteristics 2-66 revision 5 figure 2-32 ? ram write, output re tained (wmode = 0) figure 2-33 ? ram write, output as write data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (pass-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2
actel smartfusion intelligent mixed signal fpgas revision 5 2-67 figure 2-34 ? ram reset clk reset_b do d n t cyc t ckh t ckl t rstbq d m
smartfusion dc and switching characteristics 2-68 revision 5 timing characteristics table 2-85 ? ram4k9 worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.25 0.30 ns t ah address hold time 0.00 0.00 ns t ens ren_b, wen_b setup time 0.15 0.17 ns t enh ren_b, wen_b hold time 0.10 0.12 ns t bks blk_b setup time 0.24 0.28 ns t bkh blk_b hold time 0.02 0.02 ns t ds input data (di) se tup time 0.19 0.22 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (out put retained, wmode = 0) 1.81 2.18 ns clock high to new data valid on do (f low-through, wmode = 1) 2.39 2.87 ns t ckq2 clock high to new data valid on do (pipelined) 0.91 1.09 ns t c2cwwh address collision clk-to-clk delay for reliable write after write on same address?applicable to rising edge 0.30 0.35 ns t c2crwh address collision clk-to-clk delay for reliable read access after write on same address?applicable to opening edge 0.45 0.52 ns t c2cwrh address collision clk-to-clk delay for reliable write access after read on same address? applicable to opening edge 0.49 0.57 ns t rstbq reset_b low to data ou t low on do (flow-th rough) 0.94 1.12 ns reset_b low to data out low on do (pipelined) 0.94 1.12 ns t remrstb reset_b removal 0.29 0.35 ns t recrstb reset_b recovery 1.52 1.83 ns t mpwrstb reset_b minimum puls e width 0.22 0.22 ns t cyc clock cycle time 3.28 3.28 ns f max maximum clock frequency 305 305 mhz note: for the derating values at specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-69 table 2-86 ? ram512x18 worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.25 0.30 ns t ah address hold time 0.00 0.00 ns t ens ren_b, wen_b setup time 0.09 0.11 ns t enh ren_b, wen_b hold time 0.06 0.07 ns t ds input data (di) set up time 0.19 0.22 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (out put retained, wmode = 0) 2.19 2.63 ns t ckq2 clock high to new data valid on do (pipelined) 0.91 1.09 ns t c2crwh address collision clk-to-clk delay for reliable read access after write on same address?applicable to opening edge 0.50 0.58 ns t c2cwrh address collision clk-to-clk delay for reliable write access after read on same address?applicable to opening edge 0.59 0.67 ns t rstbq reset_b low to data out low on do (flow- through) 0.94 1.12 ns reset_b low to data out low on do (pipelined) 0.94 1.12 ns t remrstb reset_b removal 0.29 0.35 ns t recrstb reset_b recovery 1.52 1.83 ns t mpwrstb reset_b minimum pulse width 0.22 0.22 ns t cyc clock cycle time 3.28 3.28 ns f max maximum clock frequency 305 305 mhz note: for the derating values at specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
smartfusion dc and switching characteristics 2-70 revision 5 fifo figure 2-35 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
actel smartfusion intelligent mixed signal fpgas revision 5 2-71 timing waveforms figure 2-36 ? fifo reset figure 2-37 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
smartfusion dc and switching characteristics 2-72 revision 5 figure 2-38 ? fifo full flag and afull flag assertion figure 2-39 ? fifo empty flag and aempty flag deassertion figure 2-40 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
actel smartfusion intelligent mixed signal fpgas revision 5 2-73 timing characteristics embedded nonvolatile memory block (envm) electrical characteristics table 2-88 describes the envm maximum performance. table 2-87 ? fifo worst commercial-case conditions: t j = 85c, vcc = 1.425 v parameter description ?1 std. units t ens ren_b, wen_b setup time 1.40 1.68 ns t enh ren_b, wen_b hold time 0.02 0.02 ns t bks blk_b setup time 0.19 0.19 ns t bkh blk_b hold time 0.00 0.00 ns t ds input data (di) setup time 0.19 0.22 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.39 2.87 ns t ckq2 clock high to new data valid on do (pipelined) 0.91 1.09 ns t rckef rclk high to empty flag valid 1.74 2.09 ns t wckff wclk high to full flag valid 1.66 1.99 ns t ckaf clock high to almost empty/full flag valid 6.29 7.54 ns t rstfg reset_b low to empty/fu ll flag valid 1.72 2.06 ns t rstaf reset_b low to almost empty/ full flag valid 6.22 7.47 ns t rstbq reset_b low to data out low on do (flow-through) 0.94 1.12 ns reset_b low to data out low on do (pipelined) 0.94 1.12 ns t remrstb reset_b removal 0.29 0.35 ns t recrstb reset_b recovery 1.52 1.83 ns t mpwrstb reset_b minimum pulse width 0.22 0.22 ns t cyc clock cycle time 3.28 3.28 ns f max maximum frequency for fifo 305 305 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values. table 2-88 ? envm block timing, worst commercial case conditions: t j = 85c, vcc = 1.425 v parameter description a2f200 a2f500 units ?1 std. ?1 std. t fmaxclkenvm maximum frequency for clock for the control logic ? 6 cycles (6:1:1:1*) 80 80 50 50 mhz t fmaxclkenvm maximum frequency for clock for the control logic ? 5 cycles (5:1:1:1*) 100 80 100 80 mhz note: *6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles for the first access and 1 each for the next three accesses.
smartfusion dc and switching characteristics 2-74 revision 5 embedded flashrom (efrom) electrical characteristics table 2-89 describes the efrom maximum performance jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtai n complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/o characteristics" section on page 2-19 for more details. timing characteristics table 2-89 ? flashrom access time, worse commercial case conditions: t j = 85c, vcc = 1.425 v parameter description ?1 std. units t ck2q clock to out per configuration* 28.68 32.98 ns f max maximum clock frequency 15.00 15.00 mhz table 2-90 ? jtag 1532 worst commercial-case conditions: t j = 85c, worst-case vcc = 1.425 v parameter description ?1 std. units t disu test data input setup time 0.67 0.77 ns t dihd test data input hold time 1.33 1.53 ns t tmssu test mode select setup time 0.67 0.77 ns t tmdhd test mode select hold time 1.33 1.53 ns t tck2q clock to q (data out) 8.00 9.20 ns t rstb2q reset to q (data out) 26.67 30.67 ns f tckmax tck maximum frequency 19.00 21.85 mhz t trstrem resetb removal time 0.00 0.00 ns t trstrec resetb recovery time 0.27 0.31 ns t trstmpw resetb minimum pulse tbd tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-9 for derating values.
actel smartfusion intelligent mixed signal fpgas revision 5 2-75 programmable analog specifications current monitor unless otherwise noted, current monitor performance is specified at 25c with nominal power supply voltages, with the output measured using the internal voltage reference with the internal adc in 12-bit mode and 91 ksps, after digital compensation. all results are based on averaging over 16 samples. table 2-91 ? current monitor perfor mance specification specification test conditions min. typical max. units input voltage range (for driving adc over full range) 0 ? 48 0 ? 50 1 ? 51 mv analog gain from the differential voltage across the input pads to the adc input 50 v/v input referred offset voltage input referred offset voltage 0 0.1 0.5 mv ?40oc to +100oc 0 0.1 0.5 mv gain error slope of bfsl vs. 50 v/v 0.1 0.5 % nom. ?40oc to +100oc 0.5 % nom. overall accuracy peak error from ideal transfer function, 25c (0.1 + 0.25%) (0.4 + 1.5%) mv plus % reading input referred noise 0 vdc input (n o output averaging) 0.3 0.4 0.5 mvrms common-mode rejection ratio 0 v to 12 vdc common-mode voltage ?86 ?87 db analog settling time to 0.1% of final value (with adc load) from cm_stb (high) 5 s from adc_start (high) 5 200 s input capacitance 8pf input biased current cm[n] or tm[n] pad, ?40c to +100c over maximum input voltage range (plus is into pad) strobe = 0; ibias on cm[n] 0 a strobe = 1; ibias on cm[n] 1 a strobe = 0; ibias on tm[n] 2 a strobe = 1; ibias on tm[n] 1 a power supply rejection ratio dc (0 ? 10 khz) 41 42 db incremental operational current monitor power supply current requirements (per current monitor instance, not including adc or varefx) vcc33a 150 a vcc33ap 140 a vcc15a 50 a note: under no condition should the tm pad ever be greater than 10 mv above than the cm pad.
smartfusion dc and switching characteristics 2-76 revision 5 temperature monitor unless otherwise noted, te mperature monitor performance is spec ified with a 2n3904 diode-connected bipolar transistor from national semiconductor or infineon technologies, nominal power supply voltages, with the output measured using the internal voltage reference with the internal adc in 12-bit mode and 62.5 ksps. after digital compensation. unless otherwise noted, the specificatio ns pertain to conditions where the smartfusion device and the sens ing diode are at the same temperature. table 2-92 ? temperature monitor perf ormance specifications specification test conditions min. typical max. units input diode temperature range ?55 150 c 233.2 378.15 k temperature sensitivity 2.5 mv/k intercept extrapolated to 0k 0 v input referred temperature offset error at 25c (298.15k) 1 1.5 c gain error slope of bfsl vs. 2.5 mv/k 1 2.5 % nom. overall accuracy peak error from ideal transfer function 2 3 c input referred noise at 25c (298.15 k) ? no output averaging 4 c rms output current idle mode 100 a final measurement phases 10 a analog settling time measured to 0.1% of final value, (with adc load) from tm_stb (high) 5 s from adc_start (high) 5 105 s at parasitic capacitance 500 pf power supply rejection ratio dc (0?10 khz) 1.2 0.7 c/v input referred temperature sensitivity error variation due to device temperature (?40c to +100c). external temperature sensor held constant. 0.005 0.008 c/c temperature monitor (tm) operational power supply current requirements (per temperature monitor instance, not including adc or varefx) vcc33a 200 a vcc33ap 150 a vcc15a 50 a note: all results are based on averaging over 64 samples.
actel smartfusion intelligent mixed signal fpgas revision 5 2-77 analog-to-digital converter (adc) unless otherwise noted, adc direct input performa nce is specified at 25c with nominal power supply voltages, with the output measured us ing the external voltage reference with the internal adc in 12-bit mode and 500 khz sampling frequency, after trimming and digital compensation. figure 2-41 ? temperature error versus external capacitance -7 -6 -5 -4 -3 -2 -1 0 1 1.00e -06 1.00e -05 1.00e -04 1.00e -03 1.00e -02 1.00e -01 1.00e+00 temperature error (c) capacitance ( f) table 2-93 ? adc specifications specification test conditions min. typ. max. units input voltage range (for driving adc over its full range) 2.56 v gain error 0.4 0.7 % ?40oc to +100oc 0.4 0.7 % input referred offset voltage 1 2 mv ?40oc to +100oc 1 2 integral non-linearity (inl ) rms deviation from bfsl 12-bit mode 1.71 lsb 10-bit mode 0.60 1.00 lsb 8-bit mode 0.2 0.33 lsb differential non-linearity (dnl) 12-bit mode 2.4 lsb 10-bit mode 0.80 0.94 lsb 8-bit mode 0.2 0.23 lsb signal to noise ratio 62 64 db note: all 3.3 v supplies are tied together and varied from 3.0 v to 3.6 v. 1.5 v supplies are held constant.
smartfusion dc and switching characteristics 2-78 revision 5 effective number of bits (enob) eq 10 ?1 dbfs input 12-bit mode 10 khz 9.9 10 bits 12-bit mode 100 khz 9.9 10 bits 10-bit mode 10 khz 9.5 9.6 bits 10-bit mode 100 khz 9.5 9.6 bits 8-bit mode 10 khz 7.8 7.9 bits 8-bit mode 100 khz 7.8 7.9 bits full power bandwidth at ?3 db; ?1 dbfs input 300 khz analog settling time to 0.1% of final value (with 1 kohm source impedance and with adc load) 2s input capacitance switched capacitance (adc sample capacitor) 12 15 pf cs: static capacitance ( figure 2-42 on page 2-78 ) cm[n] input 5 7 pf tm[n] input 5 7 pf adc[n] input 5 7 pf input resistance rin: series resistance ( figure 2-42 )2k rsh: shunt resistance, exclusive of switched capacitance effects ( figure 2-42 ) 10 m input leakage current ?40c to +100c 1 a power supply rejection ratio dc 44 53 db adc power supply operational current requirements vcc33adcx 2.5 ma vcc15a 2 ma figure 2-42 ? adc input model table 2-93 ? adc specification s (continued) specification test conditions min. typ. max. units note: all 3.3 v supplies are tied together and varied from 3.0 v to 3.6 v. 1.5 v supplies are held constant. enob sinad 1.76 db ? 6.02 db/bit -------------------------------------------- - = rin rsh csw cst
actel smartfusion intelligent mixed signal fpgas revision 5 2-79 analog bipolar prescaler (abps) with the abps set to its high range setting (gdec = 00), a hypothetical input voltage in the range ?15.36 v to +15.36 v is scaled and offset by the abps input ampl ifier to match the adc full range of 0 v to 2.56 v using a nominal gain of ?0.08333 v/v. however, due to reliability considerations, the voltage applied to the abps input should never be outside the range of ?1 1.5 v to +14.4 v, restricting the usable adc input voltage to 2.238 v to 0.080 v and the corresponding 12 -bit output codes to the range of 3581 to 128 (decimal), respectively. unless otherwise noted, abps performance is specif ied at 25c with nominal power supply voltages, with the output measured using the internal voltage reference with the internal adc in 12-bit mode and 100 khz sampling frequency, after trimming and digital compensation; and applies to all ranges. table 2-94 ? abps performance specifications specification test conditions min. typ. max. units input voltage range (for driving adc over its full range) gdec[1:0] = 11 2.56 v gdec[1:0] = 10 5.12 v gdec[1:0] = 01 10.24 v gdec[1:0] = 00 (limited by maximum rating) see note 1 v analog gain (from input pad to adc input) gdec[1:0] = 11 ?0.5 v/v gdec[1:0] = 10 ?0.25 v/v gdec[1:0] = 01 ?0.125 v/v gdec[1:0] = 00 ?0.0833 v/v gain error ?2.8 ?0.4 0.7 % ?40oc to +100oc ?2.8 ?0.4 0.7 % input referred offset voltage gdec[1:0] = 11 ?0.31 ?0.07 0.31 % fr ?40oc to +100oc ?1.00 1.47 % fr gdec[1:0] = 10 ?0.34 ?0.07 0.34 % fr ?40oc to +100oc ?0.90 1.37 % fr gdec[1:0] = 01 ?0.61 ?0.07 0.35 % fr ?40oc to +100oc ?1.05 1.35 % fr gdec[1:0] = 00 ?0.39 ?0.07 0.35 % fr ?40oc to +100oc ?1.06 1.38 % fr sinad 53 56 db non-linearity rms deviation from bfsl 0.5 % fr effective number of bits (enob) eq 11 gdec[1:0] = 11 (2.56 range), ?1 dbfs input 12-bit mode 10 khz 8.6 9.1 bits 12-bit mode 100 khz 8.6 9.1 bits 10-bit mode 10 khz 8.5 8.9 bits 10-bit mode 100 khz 8.5 8.9 bits 8-bit mode 10 khz 7.7 7.8 bits 8-bit mode 100 khz 7.7 7.8 bits large-signal bandwidth ?1 dbfs input 1 mhz enob sinad 1.76 db ? 6.02 db/bit -------------------------------------------- - =
smartfusion dc and switching characteristics 2-80 revision 5 analog settling time to 0.1% of final value (with adc load) 10 s input resistance 1m power supply rejection ratio dc (0?1 khz) 38 40 db abps power supply current requirements (not including adc or varefx) abps_en = 1 (operational mode) vcc33a 123 134 a vcc33ap 89 94 a vcc15a 1 a table 2-94 ? abps performance specifi cations (continued) specification test conditions min. typ. max. units
actel smartfusion intelligent mixed signal fpgas revision 5 2-81 comparator unless otherwise specified, performance is specif ied at 25c with nominal power supply voltages. table 2-95 ? comparator performance specifications specification test conditions min. typ. max. units input voltage range minimum 0 v maximum 2.56 v input offset voltage hys[1:0] = 00 (no hysteresis) 1 3 mv input bias current comparator 1, 3, 5, 7, 9 (measured at 2.56 v) 40 60 na comparator 0, 2, 4, 6, 8 (measured at 2.56 v) 150 300 na input resistance 10 m power supply rejection ratio dc (0 ? 10 khz) 50 60 db propagation delay 100 mv overdrive hys[1:0] = 00 (no hysteresis) 15 18 ns 100 mv overdrive hys[1:0] = 10 (with hysteresis) 25 30 ns hysteresis ( refers to rising and falling threshold shifts, respectively) hys[1:0] = 00 ?5 0 5 mv ?40oc to +100oc ?5 5 mv hys[1:0] = 01 3 16 30 mv ?40oc to +100oc 0 36 mv hys[1:0] = 10 19 31 48 mv ?40oc to +100oc 12 54 mv hys[1:0] = 11 80 105 190 mv ?40oc to +100oc 80 194 mv comparator current requirements (per comparator) vcc33a = 3.3 v (operational mode); comp_en = 1 vcc33a 150 165 a vcc33ap 140 165 a vcc15a 1 3 a
smartfusion dc and switching characteristics 2-82 revision 5 analog sigma-delta digital to analog converter (dac) unless otherwise noted, sigma-delta dac performanc e is specified at 25c with nominal power supply voltages, using the internal sigma-delta modulat ors with 16-bit inputs, hclk = 100 mhz, modulator inputs updated at a 100 khz rate, in voltage output mode with an external 160 pf capacitor to ground, after trimming and digital [pre-]compensation. table 2-96 ? analog sigma-delta dac specification test conditions min. typ. max. units resolution 8 24 bits output range 0 to 2.56 v current output mode 0 to 256 a output impedance 6 10 12 k current output mode 10 m output voltage compliance current output mode 0?3.0 v ?40oc to +100oc 0?2.7 0?3.4 gain error voltage output mode 0.3 2 % a2f200: ?40oc to +100oc 1.2 5.3 % a2f500: ?40oc to +100oc 0.3 2 % current output mode 0.3 2 % a2f200: ?40oc to +100oc 1.2 5.3 % a2f500: ?40oc to +100oc 0.3 2 % output referred offset dac byte0 = h?00 (8-bit) 0.25 1 mv ?40oc to +100oc 1 2.5 mv current output mode 0.3 1 a ?40oc to +100oc 1 2.5 a integral non-linearity rms de viation from bfsl 0.1 0.3 % fr differential non-linearity 0.05 0.4 % fr analog settling time refer to figure 2-43 on page 2-83 s power supply rejection ratio dc, full scale output 33 34 db sigma-delta dac power supply current requirements (not including varefx) input = 0, en = 1 (operational mode) vcc33sddx 30 35 a vcc15a 3 5 a input = half scale, en = 1 (operational mode) vcc33sddx 160 165 a vcc15a 33 35 a input = full scale, en = 1 (operational mode) vcc33sddx 280 285 a vcc15a 70 75 a
actel smartfusion intelligent mixed signal fpgas revision 5 2-83 figure 2-43 ? sigma-delta dac setting time 0 0123 4 56 78 910324864128255 20 40 60 80 100 120 140 160 180 200 220 settling t ime (us) input code sigma delta dac settling time
smartfusion dc and switching characteristics 2-84 revision 5 voltage regulator table 2-97 ? voltage regulator symbol parameter test conditions min. typ. max. unit v out output voltage t j = 25c 1.425 1.5 1.575 v v os output offset voltage t j = 25c 11 mv icc33a operation current t j = 25c i load = 1 ma 3.4 ma i load = 100 ma 11 ma i load = 0.5 a 21 ma v out load regulation t j = 25c i load = 1 ma to 0.5 a 5.8 mv v out line regulation t j = 25c vcc33a = 2.97 v to 3.63 v i load = 1 ma 5.3 mv/v vcc33a = 2.97 v to 3.63 v i load = 100 ma 5.3 mv/v vcc33a = 2.97 v to 3.63 v i load = 500ma 5.3 mv/v dropout voltage 1 t j = 25c i load = 1 ma 0.63 v i load = 100 ma 0.84 v i load = 0.5 a 1.35 v i ptbase ptbase current t j = 25c i load = 1 ma 48 a i load = 100 ma 736 a i load = 0.5 a 12 ma startup time 2 t j = 25c 200 ms notes: 1. dropout voltage is defined as the minimum vcc33a voltage. the parameter is specified with respect to the output voltage. the specification represents the minimum input-to-output differential voltage required to maintain regulation. 2. assumes 10 f.
actel smartfusion intelligent mixed signal fpgas revision 5 2-85 figure 2-44 ? typical output voltage figure 2-45 ? load regulation load = 10 ma load = 100 ma load = 500 ma -0.025 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 -40-20 0 20406080100 offset voltage (v) temperature (c) typical output voltage -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -40 -20 0 20 40 60 80 100 change in output voltage with load (mv) temperature (c) load regulation
smartfusion dc and switching characteristics 2-86 revision 5 serial peripheral interface (spi) characteristics this section describes the dc and switching of th e spi interface. unless otherwise noted, all output characteristics given for a 35 pf load on the pins and all sequential timing characteristics are related to spi_x_clk. for timing parameter definitions, refer to figure 2-46 on page 2-87 . table 2-98 ? spi characteristics commercial case conditions: t j = 85oc, vdd = 1.425 v, ?1 speed grade symbol description and condition a2f200 a2f500 unit sp1 spi_x_clk minimum period spi_x_clk = pclk/2 na 20 ns spi_x_clk = pclk/4 40 40 ns spi_x_clk = pclk/8 80 80 ns spi_x_clk = pclk/16 0.16 0.16 s spi_x_clk = pclk/32 0.32 0.32 s spi_x_clk = pclk/64 0.64 0.64 s spi_x_clk = pclk/128 1.28 1.28 s spi_x_clk = pclk/256 2.56 2.56 s sp2 spi_x_clk minimum pulse width high spi_x_clk = pclk/2 na 10 ns spi_x_clk = pclk/4 20 20 ns spi_x_clk = pclk/8 40 40 ns spi_x_clk = pclk/16 0.08 0.08 s spi_x_clk = pclk/32 0.16 0.16 s spi_x_clk = pclk/64 0.32 0.32 s spi_x_clk = pclk/128 0.64 0.64 s spi_x_clk = pclk/256 1.28 1.28 us sp3 spi_x_clk minimum pulse width low spi_x_clk = pclk/2 na 10 ns spi_x_clk = pclk/4 20 20 ns spi_x_clk = pclk/8 40 40 ns spi_x_clk = pclk/16 0.08 0.08 s spi_x_clk = pclk/32 0.16 0.16 s spi_x_clk = pclk/64 0.32 0.32 s spi_x_clk = pclk/128 0.64 0.64 s spi_x_clk = pclk/256 1.28 1.28 s sp4 spi_x_clk, spi_x_do, spi_x_ss rise time (10%-90%) 1 4.7 4.7 ns sp5 spi_x_clk, spi_x_do, spi_x_ss fall time (10%-90%) 1 3.4 3.4 ns notes: 1. these values are provided for a load of 35 pf. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the microsemi soc products group website: http://www.actel.com/download/ibis/default.aspx . 2. for allowable pclk configurations, refer to the serial peripheral interface controller section in the smartfusion microcontroller subsystem user?s guide .
actel smartfusion intelligent mixed signal fpgas revision 5 2-87 sp6 data from master (spi_x_do) setup time 2 1 1 pclk cycles sp7 data from master (spi_x_do) hold time 2 1 1 pclk cycles sp8 spi_x_di setup time 2 1 1 pclk cycles sp9 spi_x_di hold time 2 1 1 pclk cycles figure 2-46 ? spi timing for a single frame tran sfer in motorola mode (sph = 1) table 2-98 ? spi characteristics commercial case conditions: t j = 85oc, vdd = 1.425 v, ?1 speed grade (continued) symbol description and condition a2f200 a2f500 unit notes: 1. these values are provided for a load of 35 pf. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the microsemi soc products group website: http://www.actel.com/download/ibis/default.aspx . 2. for allowable pclk configurations, refer to the serial peripheral interface controller section in the smartfusion microcontroller subsystem user?s guide . spi_x_clk spo = 0 spi_x_do sp6 sp7 50% 50% msb 50% 50% 50% sp2 sp1 90% 10% 10% sp4 sp5 sp8 sp9 50% 50% msb spi_x_di 10% 90% sp5 90% 10% sp4 90% 10% 10% sp4 sp5 90% spi_x_ss spi_x_clk spo = 1 sp3
smartfusion dc and switching characteristics 2-88 revision 5 inter-integrated circuit (i 2 c) characteristics this section describes the dc and switching of the i 2 c interface. unless otherwise noted, all output characteristics given are for a 100 pf load on the pins. for timing parameter definitions, refer to figure 2- 47 on page 2-89 . table 2-99 ? i 2 c characteristics commercial case conditions: t j = 85oc, v dd = 1.425 v, ?1 speed grade parameter definition condition value unit v il minimum input low voltage ? see table 2-35 on page 2-30 ? maximum input low voltage ? see ta b l e 2 - 3 5 ? v ih minimum input high voltage ? see ta b l e 2 - 3 5 ? maximum input high voltage ? see ta b l e 2 - 3 5 ? v ol maximum output voltage low i ol =8ma see ta b l e 2 - 3 5 ? i il input current high ? see ta b l e 2 - 3 5 ? i ih input current low ? see ta b l e 2 - 3 5 ? v hyst hysteresis of schmitt trigger inputs ? see table 2-32 on page 2-29 v t fall fall time 2 vihmin to vilmax, c load = 400 pf 15.0 ns vihmin to vilmax, c load = 100 pf 4.0 ns t rise rise time 2 vilmax to vihmin, c load = 400pf 19.5 ns vilmax to vihmin, c load = 100pf 5.2 ns cin pin capacitance vin = 0, f = 1.0 mhz 8.0 pf r pull-up output buffer maximum pull- down resistance 1 ?50 r pull-down output buffer maximum pull-up resistance 1 ? 150 d max maximum data rate fast mode 400 kbps t low low period of i2c_x_scl 3 ? 1 pclk cycles t high high period of i2c_x_scl 3 ? 1 pclk cycles t hd;sta start hold time 3 ? 1 pclk cycles t su;sta start setup time 3 ? 1 pclk cycles t hd;dat data hold time 3 ? 1 pclk cycles t su;dat data setup time 3 ? 1 pclk cycles notes: 1. these maximum values are provided for information only. minimum output buffer resistance values depend on vccxxxxiobx, drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the soc products group website at http://www.actel.com/download/ibis/default.aspx . 2. these values are provided for a load of 100 pf and 400 pf. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the soc products group website at http://www.actel.com/download/ibis/default.aspx . 3. for allowable pclk configurations, refer to the inter-integrated circuit (i 2 c) peripherals section in the smartfusion microcontroller subsystem user?s guide .
actel smartfusion intelligent mixed signal fpgas revision 5 2-89 t su;sto stop setup time 3 ? 1 pclk cycles t filt maximum spike width filtered ? 50 ns figure 2-47 ? i2c timing parameter definition table 2-99 ? i 2 c characteristics commercial case conditions: t j = 85oc, v dd = 1.425 v, ?1 speed grade (continued) parameter definition condition value unit notes: 1. these maximum values are provided for information only. minimum output buffer resistance values depend on vccxxxxiobx, drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the soc products group website at http://www.actel.com/download/ibis/default.aspx . 2. these values are provided for a load of 100 pf and 400 pf. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the soc products group website at http://www.actel.com/download/ibis/default.aspx . 3. for allowable pclk configurations, refer to the inter-integrated circuit (i 2 c) peripherals section in the smartfusion microcontroller subsystem user?s guide . scl t rise t fall t low t hd;sta sda t high t hd;dat t su;dat t su;sto t su;sta s p

revision 5 3-1 3 ? smartfusion development tools smartfusion applications will be developed by a mult i-discipline team of designers working on one project or one designer acting in several roles. the microsemi soc products group has developed design tools and flows to meet the needs of three different skilled designers that can work smoothly together in a single project ( figure 3-1 ). ? fpga designers ? embedded software designers ? analog designers for fpga designers, libero ? integrated design environment (ide ) is microsemi soc product group's comprehensive toolset for designing with all soc pr oducts group fpgas. libero ide includes industry leading synthesis, simulation, and place-and-route debug tools, including synplicity ? and modelsim, ? as well as innovative timing, power optimization, and power analysis. for embedded designers, the soc products group offe rs free softconsole eclipse-based ide, as well as evaluation versions from keil? and iar systems. fu ll versions of the latter are available from the respective suppliers. for analog design ers, the microcontroller subsystem (mss) co nfigurator provides graphical setup for current, voltage, and temperature monitors, sample sequencing setup and post processing configuration, and dac output. the mss configurator creates a bridge betw een the fpga and embedded designers so device configuration can be easily shared between multiple developers. figure 3-1 ? three design roles fpga design embedded design mss configurator mss configuration ? analog configuration hardware interfaces flashpro4, ulink, j-link design entry, ip library simulation, synthesis compile, layout timing, power analysis hardware debug drivers, sample projects application development build project simulation software debug
smartfusion development tools 3-2 revision 5 the mss configurator includes the following: ? a simple configurator for the embedded desi gner to control the mss peripherals and i/os ? a method to import and view a hardware config uration from the fpga flow into the embedded flow containing the memory map ? automatic generati on of drivers for any periphe rals or soft ip used in the system configuration ? comprehensive analog configuration for the programmable analog components ? creation of a standard mss block to be used in smartdesign for connection of fpga fabric designs and ip smartfusion ecosystem the soc products group has a long history of supplying comprehensive fpga development tools and recognizes the benefit of partnering with industry leaders to deliver the optimum usability and productivity to users. taking the same appr oach to processor development, the soc products group has partnered with key industry leaders in the microcontroller spac e to provide a robust solution that can be easily adopted by existing embedded developers and has an easy learning path for fpga designers. the soc products group is partnering with keil and iar to provide software ide support to smartfusion designers. in addition, micrium provides suppor t for smartfusion with its new c/os-iii,? tcp/ip,? and c/probe? products ( table 3-1 on page 3-3 ). support for the soc products group device and ecosystem resources is represented in figure 3-2 . starting from the base up, the arm ? cortex? microcontroller softwa re interface standard (cmsis) hardware abstraction layer (hal) is built on top of the smartfusion hardware platform. each of the peripherals has its own driver, whether it is hard ip or soft ip added in the fpga fabric. then on top of that we will work with third party real-time operating system (rtos) ve ndors for os, protocol stacks, and interfaces. a designer can add a custom application with all, some, or none of the layers below. figure 3-2 ? smartfusion ecosystem 1 2 c driver spi driver uart driver ethernet driver timer driver nvm driver application layer protocol stacks, file systems, interfaces rtos ? real-time operating system hardware abstraction layer target hardware platform customer alogorithms/ intellectual property third party tcp, http, smtp dhcp, lcd third party c/osii actel or third party for hard ip or soft ip i 2 c, spi, uart, nvm ram, 10/100, timer actel cmsis-based actel smartfusion application code hal physical layer middleware rtos drivers
smartfusion intelligent mixed signal fpgas revision 5 3-3 software integrated design environment (ide) choices operating system and middleware support micrium is recognized as a leader in embedded so ftware components. the company's flagship c/os family is recognized for a variety of features and benefits, including unparalleled reliability, performance, dependability, impeccable source code, and vast documentation, available from www.micrium.com software ide softconsole vision ide embedded workbench website www.actel.com www.keil.com www.iar.com free versions from soc products group free with libero ide 32 k code limited 32 k code limited available from vendor n/a full version full version compiler gnu gcc realview c/c++ iar arm compiler debugger gdb debug vision debugger c-spy debugger instruction set simulator no vision simulator yes debug hardware flashpro4 ulink2 or ulink-me j-link or j-link lite table 3-1 ? micrium embedded software components c/os-iii,? micrium's newest rtos, is designed to save time on your next embedded project and puts greater control of the software in your hands, yet maintains micrium's ease-of-use, ease-of-integration, short learning curve, unsurpassed documentation, and clean code. c/tcp-ip? is a compact, reliable, and high-performance stack built from the ground up by micrium and has the quality, scalability, and reliability that translates into a rapid configuration of network options, remarkable ease-of- use, and rapid time-to-market. c/probe? is one of the most useful tools in embedded systems design and puts you in the driver's seat, allowing you to take charge of virtually any variable, memory location, and i/o port in your embedded product, while your system is running?there's no need to stop.

revision 5 4-5 4 ? smartfusion programming smartfusion devices have three separate flash areas that can be programmed: 1. the fpga fabric 2. the embedded nonvolatile memories (envms) 3. the embedded flash rom (efrom) there are essentially three methodol ogies for programming these areas: 1. in-system programming (isp) 2. in-application programming (iap)?o nly the fpga fabric and the envm 3. pre-programming (non-isp) programming, whether isp or iap methodologies are employed, can be done in two ways: 1. securely using the on chip aes decryption logic 2. in plain text in-system programming in-system programming is performed with the aid of external jtag programming hardware. table 4-1 describes the jtag programming hardware th at will program a smartfusion device and table 4-2 defines the jtag pins that provide the interface for the programming hardware. table 4-1 ? supported jtag programming hardware dongle source jtag swd 1 swv 2 program fpga program efrom program envm flashpro3/4 soc products group yes no no yes yes yes ulink pro keil yes yes yes yes 3 yes 3 yes ulink2 keil yes yes yes yes 3 yes 3 yes iar j-link iar yes yes yes yes 3 yes 3 yes notes: 1. swd = arm serial wire debug 2. swv = arm serial wire viewer 3. planned support table 4-2 ? smartfusion jtag pin descriptions pin name description jtagsel arm cortex-m3 or fpga test access port (tap) controller selection trstb test reset bar tck test clock tms test mode select tdi test data input tdo test data output
smartfusion programming 4-6 revision 5 the jtagsel pin selects the fpga tap controller or the cortex-m3 debug logic. when jtag sel is asserted, the fpga tap controller is selected and the trstb input into the cortex-m3 is held in a reset state (logic 0), as depicted in figure 4-1 . users should tie the jtagsel pin high externally. note: standard arm jtag connectors do not have access to the jtagsel pin. soc product group?s free eclipse-based ide, softconsole, automatical ly selects the appropriate tap controller using the ctxselect jtag command. when using softconsole, the st ate of jtagsel is a "don't care." in-application programming in-application programming refers to the ability to reprogram the various flash areas under direct supervision of the cortex-m3. reprogramming the fpga fa bric using the cortex-m3 in this mode, the cortex-m3 is executing the programming algorithm on-chip. the iap driver can be incorporated into the design proj ect and executed from envm or esram. the soc products group provides working example projects for softconsol e, iar, and keil development environments. these can be downloaded via the soc products group firmware catalog. the new bitstream to be programmed into the fpga can reside on the user?s printed circuit board (pcb) in a separate spi flash memory. alternately, the user can modify the existing projects supplied by the soc products group and, via custom handshaking software, throttle the dow nload of the new image and program the fpga a piece at a time in real time. a cost-effective and reliable approach would be to store the bitstream in an external spi flash. another option is storing a redu ndant bitstream image in an external spi flash and loading the newest version into the fpga only wh en receiving an iap command. since the fpga i/os are tristated or held at predefined or last known st ate during fpga programming, the user must use mss i/os to interface to external memories. since ther e are two spi controllers in the mss, the user can dedicate one to an spi flash and the other to the particulars of an applicat ion. the amount of flash memory required to program the fpga always exceeds the size of the envm block that is on-chip. the external memory controller (emc) cannot be used as an interface to a memory device for storage of a bitstream because its i/o pads are fpga i/os; h ence they are tristated w hen the fpga is in a programming state. figure 4-1 ? trstb logic jtag_sel trstb cortex-m3 tap controller fpga programming control fpga tap controller trstb vjtag (1.5 v to 3.3. v nominal)
smartfusion intelligent mixed signal fpgas revision 5 4-7 re-programming the envm bl ocks using the cortex-m3 in this mode the cortex-m3 is ex ecuting the envm programming algorithm from esram. since individual pages (132 bytes) of the envm can be write-prot ected, the programming algorithm software can be protected from inadvertent erasure. when reprogramming the envm , both mss i/os and fpga i/os are available as interfaces for sourcing the new envm image. the soc products group provides working example projects for softconsole, iar, and keil development environments. these can be downloaded via the soc products group firmware catalog. alternately, the envm can be reprogrammed by the co rtex-m3 via the iap driver. this is necessary when using an encrypted image. secure programming for background, refer to the security in low power flash devices application note on the soc products group website. smartfusion secure isp behaves identically to fusion secure isp. secure iap of smartfusion devices is accomplished by using the i ap driver. only the fpga fabric and the envm can be reprogrammed securely by using the iap driver. typical programming and erase times table 4-3 documents the typical programming and eras e times for two components of smartfusion devices, fpga fabric and envm, using the soc pr oducts group?s flashpro hardware and software. these times will be different for other isp and iap methods. the program action in flashpro software includes erase, program, and verify to complete. the typical programming (including erase) time per page of the envm is 8 ms. references user?s guides directc user?s guide http://www.actel.com/documents/directc_ug.pdf fusion fgpa fabric user?s guide http://www.actel.com/documents/fusion_ug.pdf chapters: "in-system programming (isp) of actel?s lo w-power flash devices using flashpro4/3/3x" "security in low po wer flash devices" "programming flash devices" "microprocessor programming of actel?s low-power flash devices" table 4-3 ? typical programming and erase times fpga fabric (seconds) envm (seconds) a2f200 a2f500 a2f200 a2f500 erase 21 21 n/a n/a program 8 15 18 26 verify 9 16 26 42

revision 5 5-1 smartfusion intelligent mixed signal fpgas 5 ? pin descriptions supply pins name type description gnd ground digital ground to the fpga f abric, microcontroller subsystem and gpios gnd15adc0 ground quiet analog ground to the 1.5 v circ uitry of the first analog-to-digital converter (adc) gnd15adc1 ground quiet analog ground to the 1.5 v circuitry of the second adc gnd15adc2 ground quite analog ground to the 1.5 v circuitry of the third adc gnd33adc0 ground quiet analog ground to the 3.3 v circuitry of the first adc gnd33adc1 ground quiet analog ground to the 3.3 v circuitry of the second adc gnd33adc2 ground quiet analog ground to the 3.3 v circuitry of the third adc gnda ground quiet analog ground to the analog front-end gndaq ground quiet analog ground to the analog i/o of smartfusion devices gndenvm ground digital ground to the embedded nonvolatile memory (envm) gndlpxtal ground analog ground to the low power 32 khz crystal oscillator circuitry gndmainxtal ground analog ground to the main crystal oscillator circuitry gndq ground quiet digital ground supply voltage to input buffers of i/o banks. within the package, the gndq plane is decoupled from the simulta neous switching noise originated from the output buffer ground domain. this minimize s the noise transfer within the package and improves input signal integrity. gndq needs to always be connected on the board to gnd. gndrcosc ground analog ground to the integrated rc oscillator circuit gndsdd0 ground analog ground to the first sigma-delta dac gndsdd1 ground common analog ground to the second and third sigma-delta dacs gndtm0 ground analog temperature monitor common ground for signal conditioning blocks scb 0 and scb 1 (see information for pins "tm0" and "tm1" in the "analog front-end (afe)" section on page 5-12 ). gndtm1 ground analog temperature monitor common ground for signal conditioning block scb 2 and sbcb 3 (see information for pins "tm2" and "tm3" in the "analog front-end (afe)" section on page 5-12 ). gndtm2 ground analog temperature monitor common ground for signal conditioning block scb4 gndvaref ground analog ground reference used by th e adc. this pad should be connected to a quiet analog ground. vcc supply digital supply to the fpga fabric and ms s, nominally 1.5 v. vcc is also required for powering the jtag state machine, in addition to v jtag . even when a smartfusion device is in bypass mode in a jtag chai n of interconnected devices, both vcc and v jtag must remain powered to allow jtag signals to pass through the smartfusion device. notes: 1. the following 3.3 v supplies should be connected together while following proper noise filtering practices: vcc33a, vcc33adcx, vcc33ap, vcc33sddx, vccmainxtal, and vcclpxtal. 2. the following 1.5 v supplies should be connected together while following proper noise filtering practices: vcc, vcc15a, and vcc15adcx.
pin descriptions 5-2 revision 5 vcc15a supply clean analog 1.5 v supply to the analog circuitry vcc15adc0 supply analog 1.5 v supply to the first adc vcc15adc1 supply analog 1.5 v supply to the second adc vcc15adc2 supply analog 1.5 v supply to the third adc vcc33a supply clean 3.3 v analog supply to the analog circuitry. vcc33a is also used to feed the 1.5 v voltage regulator for designs that do no t provide an external supply to vcc. refer to the voltage regulator (vr), power supply monitor (psm), and power modes section in the smartfusion microcontrolle r subsystem user?s guide for more information. vcc33adc0 supply analog 3.3 v supply to the first adc. vcc33adc1 supply analog 3.3 v supply to the second adc vcc33adc2 supply analog 3.3 v supply to the third adc vcc33ap supply analog clean 3.3 v supply to the char ge pump. to avoid high current draw, vcc33ap should be powered up simultaneously with or after vcc33a. vcc33n supply ?3.3 v output from the voltage conver ter. a 2.2 f capacitor must be connected from this pin to gnd. analog charge pump capa citors are not needed if none of the analog scb features are used and none of the sdds are used. in that case it should be left unconnected. vcc33sdd0 supply analog 3.3 v supply to the first sigma-delta dac vcc33sdd1 supply common analog 3.3 v supply to the second and third sigma-delta dacs vccenvm supply digital 1.5 v power supply to the embedded nonvolatile memory blocks. to avoid high current draw, vcc should be powered up before or simultaneously with vccenvm. vccfpgaiob0 supply digital supply to the fpga fabric i/o bank 0 (n orth fpga i/o bank) for the output buffers and i/o logic. each bank can have a separate vccfpgaio connection. all i/os in a bank will run off the same vccfpgaio supply. vccfpgaio can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vccfpgaio pins tied to gnd. vccfpgaiob1 supply digital supply to the fpga fabric i/o bank 1 (east fpga i/o bank) for the output buffers and i/o logic. vccfpgaiob5 supply digital supply to the fpga fabric i/o bank 5 (west fpga i/o bank) for the output buffers and i/o logic. each bank can have a separate vccfpgaio connection. all i/os in a bank will run off the same vccfpgaio supply. vccfpgaio can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vccfpgaio pins tied to gnd. each bank can have a separate vccfpgaio connection. all i/os in a bank will run off the same vccfpgaio supply. vccfpgaio can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vccfpgaio pins tied to gnd. vcclpxtal supply analog supply to the low power 32 khz crystal oscillator vccmainxtal supply analog supply to the main crystal oscillator circuit name type description notes: 1. the following 3.3 v supplies should be connected together while following proper noise filtering practices: vcc33a, vcc33adcx, vcc33ap, vcc33sddx, vccmainxtal, and vcclpxtal. 2. the following 1.5 v supplies should be connected together while following proper noise filtering practices: vcc, vcc15a, and vcc15adcx.
smartfusion intelligent mixed signal fpgas revision 5 5-3 vccmssiob2 supply supply voltage to t he microcontroller subsystem i/o b ank 2 (east mss i/o bank) for the output buffers and i/o logic vccmssiob4 supply supply voltage to the microcontroller subsystem i/o ban k 4 (west mss i/o bank) for the output buffers and i/o logic. each bank can have a separate vccmssio connection. all i/os in a bank will run off the same vccmssio supply. vccmssio can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have t heir corresponding vccmssio pins tied to gnd. each bank can have a separate vccmssio connection. all i/os in a bank will run off the same vccmssio supply. vccmssio can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have t heir corresponding vccmssio pins tied to gnd. vccpllx supply analog 1.5 v supply to the pll vccrcosc supply analog supply to the integrated rc oscillator circuit vcomplax supply analog ground for the pll vddbat supply external battery connection to the low power 32 khz crystal oscillator (along with vcclpxtal), rtc, and battery switchover circuit vjtag supply digital supply to the jtag controller smartfusion devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned to be used, the v jtag pin together with the trstb pin c ould be tied to gnd. note that vcc is required to be powered for jtag operation; vjtag alone is insufficient. if a smartfusion device is in a jtag chain of interconnected boards and it is desired to power down the board containing the device, this can be done provided both vjtag and vcc to the device remain powered; othe rwise, jtag signals will not be able to transition the device, even in bypass mode. see "jtag pins" section on page 5-8 . vpp supply digital programming circuitry supply smartfusion devices support single-volt age in-system programming (isp) of the configuration flash, embedded flashrom (efrom), and embedded nonvolatile memory (envm). for programming, vpp should be in the 3.3 v 5% range. during normal device operation, vpp can be left float ing or can be tied to any vo ltage between 0 v and 3.6 v. when the vpp pin is tied to gr ound, it shuts off the charge pu mp circuitry, resulting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacitors (both rated at 16 v) are to be connected in parallel across vpp and gnd, and positioned as close to the fpga pins as possible. name type description notes: 1. the following 3.3 v supplies should be connected together while following proper noise filtering practices: vcc33a, vcc33adcx, vcc33ap, vcc33sddx, vccmainxtal, and vcclpxtal. 2. the following 1.5 v supplies should be connected together while following proper noise filtering practices: vcc, vcc15a, and vcc15adcx.
pin descriptions 5-4 revision 5 user-defined supply pins name type polarity/bus size description varef0 input 1 analog reference voltage for first adc the smartfusion device can be configured to generate a 2.56 v internal reference that can be used by th e adc. while using the internal reference, the reference voltage is output on the vare fout pin for use as a system reference. if a different reference voltage is required, it can be supplied by an external source and applied to this pin. the valid range of values that can be supplied to the adc is 1.0 v to 3.3 v. when varef0 is internally generated, a bypass capacitor must be connected from this pin to ground. the value of the bypass capacitor should be between 3.3 f and 22 f, which is based on the needs of the individual designs. the choice of the capacito r value has an impact on the settling time it takes the varef0 signal to r each the required specification of 2.56 v to initiate valid conversions by the adc. if the lower capacitor value is chosen, the settling time required for varef0 to achieve 2.56 v will be shorter than when selecting the larger capacitor value. the above range of capacitor values supports the accu racy specification of the adc, which is detailed in the datasheet. designers choosing the smaller capacitor value will not obtain as much margin in the accuracy as that achieved with a larger capacitor value. see the analog-to-digital converter (adc) section in the smartfusion programmable analog user?s guide for more information. the soc products group recommends customers use 10 f as the value of the bypass capacitor. designers choosing to use an external varef0 need to ensure that a stable and clean varef0 source is supplied to the varef0 pin before initiating conversions by the adc. to use the internal voltage reference, you must connect the varefout pin to the appropriate adc varefx input?either the varef0 or varef1 pin?on the pcb. varef1 input 1 analog reference voltage for second adc see "varef0" above for more information. varef2 input 1 analog reference voltage for third adc see "varef0" above for more. varefout out 1 internal 2.56 v voltage refer ence output. can be used to provide the two adcs with a unique voltage reference externally by connecting varefout to both varef0 and varef1. to use the internal voltage reference, you must connect the va refout pin to the appropriate adc varefx input?either the varef0 or varef1 pin?on the pcb.
smartfusion intelligent mixed signal fpgas revision 5 5-5 user pins name type polarity/bus size description gpio_x in/out 32 microcontroller subsystem (mss) general purpose i/o (gpio). the mss gpio pin functions as an input, output, tristate, or bidirectional buffer with configurable interrupt generation and schmitt trigger support. input and output signal levels are compatible with the i/o standard selected. unused gpio pins are tristated an d do not include pull-up or pull-down resistors. during power-up, the used gpio pi ns are tristated with no pull-up or pull-down resistors until s ys boot configures them. some of these pins are also multiple xed with integrated peripherals in the mss (spi, i 2 c, and uart). gpios can be routed to dedicated i/o buffers (mssiobuf) or in some cases to the fpga fabric interface through an iomux. this allows gpio pins to be multiplexed as either i/os for the fpga fabric, the arm ? cortex?-m3 or for given integrated mss peripherals. the mss peripherals are not multiplexed with each other; they are multiplexed only with the gpio block. for more information, see t he general purpose i/o block (gpio) section in the smartfusion microcontroller subsystem user?s guide . io in/out fpga user i/o the fpga user i/o pin functions as an input, output, tristate or bidirectional buffer. input and output signal levels are compatible with the i/o standard selected. unused i/o pins are disabled by libero ide software and include a weak pull-up resistor. during power-up, the used i/o pins are tristated with no pull-up or pull-down resistors un til i/o enable (there is a delay after voltage stabilizes, and di fferent i/o banks power up se quentially to avoid a surge of icci). some of these pins are also multiple xed with integrated peripherals in the mss (ethernet mac and exte rnal memory controller). during programming, i/os become tr istated and weakly pulled up to vcci. with the vcci and vcc supplies continuously powered up, when the device transitions from programming to oper ating mode, the i/os are instantly configured to the desired user config uration. for more information, see the smartfusion fpga user i/os section in the smartfusion fpga fabric user?s guide . the naming convention used for each fpga user i/o is: iouxwbyvz where: u = i/o pair number in bank, starting at 00 from the northwest i/o bank and incrementing clockwise. x = p (positive) or n (negative) or s (single-ended) or r (regular, single- ended). w = d (differential pair) or p (pair) or s (single-ended) or r (regular, single- ended). y = bank number starting at 0 from northwest i/o bank and incrementing clockwise. z = v ref mini bank number.
pin descriptions 5-6 revision 5 special function pins name type polarity/bus size description nc no connect this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. dc do not connect. this pin should not be connected to any signals on the pcb. these pins should be left unconnected. lpxin in 1 low power 32 khz crystal oscillator. input from the 32 khz oscillator. pin for connecting a low power 32 khz watch crystal. if not used, the l pxin pin can be left floating. for more information, see the plls, clock conditioning circuitry, and on- chip crystal oscillators section in the smartfusion microcontroller subsystem user?s guide . lpxout in 1 low power 32 khz crystal oscillator. output to the 32 khz oscillator. pin for connecting a low power 32 khz watch crystal. if not used, the lpxout pin can be left floating. for more information, see the plls, clock conditioning circuitry, and on- chip crystal oscillators section in the smartfusion microcontroller subsystem user?s guide . mainxin in 1 main crystal oscillator circuit. input to the crystal oscillator circuit. pin for connecting an external crystal, ceramic resonator, or rc network. when using an external crystal or ceramic oscillator, external capacitors are also recommended. refer to documentation from the crystal oscillator manufacturer for proper capacitor value. if using an external rc network or clock input, mainxin should be used and mainxout left unconnected. for more information, see the plls, clock conditioning circuitry, and on-chip crystal oscillators section in the smartfusion microcontroller subsystem user?s guide . mainxout out 1 main crystal oscillator circuit. output from the crystal oscillator circuit. pin for connecting external crystal or ceramic resonator. when using an external crystal or ceramic oscillator, external capacitors are also recommended. refer to documentation from the crystal oscillator manufacturer for proper capacitor value. if using external rc network or clock input, mainxin should be used and mainxout left unconnected. fo r more information, see the plls, clock conditioning circuitry, and on-chip crystal oscillators section in the smartfusion microcontrolle r subsystem user?s guide . ncap 1 negative capacitor connection. this is the negative terminal of the charge pump. a capacitor, with a 2.2 f recommended value, is required to connect between pcap and ncap. analog charge pump capacito rs are not needed if none of the analog scb features are used and none of the sdds are used. in that case it should be left unconnected.
smartfusion intelligent mixed signal fpgas revision 5 5-7 pcap 1 positive capacitor connection. this is the positive terminal of the charge pump. a capacitor, with a 2.2 f recommended value, is required to connect between pcap and ncap. if this pin is not used, it must be left unconnected/floating. in this case, no capacitor is needed. analog charge pump capacitors are not needed if none of the analog scb fe atures are used, and none of the sdds are used. ptbase 1 pass transistor base connection this is the control signal of the voltage regulator. this pin should be connected to the base of an external pass transistor used with the 1.5 v internal voltage regulator and can be floating if not used. ptem 1 pass transistor emitter connection. this is the feedback input of the voltage regulator. this pin should be connected to the emitter of an external pass transistor used with the 1.5 v internal voltage regulator and can be floating if not used. mss_reset_n in low reset signal fo r the microcontroller subsystem. pu_n in low push-button is the connection fo r the external momentary switch used to turn on the 1.5 v voltage regulator and can be floating if not used. name type polarity/bus size description
pin descriptions 5-8 revision 5 jtag pins smartfusion devices have a separate bank for t he dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). vcc mu st also be powered for the jtag state machine to operate, even if the device is in bypass mode; vjtag alone is insufficient. both vjtag and vcc to the smartfusion part must be supplied to allow jtag si gnals to transition the smartfusion device. isolating the jtag power supply in a separate i/o bank gives greater flexibility with suppl y selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned to be used, the vjtag pin together with the trstb pin could be tied to gnd. name type polarity/ bus size description jtagsel in 1 jtag controller selection depending on the state of the jtagsel pin, an external jtag controller will either see the fpga fabric tap/auxiliary tap (high) or the cortex-m3 jtag debug interface (low). the jtagsel pin should be connected to an external pull-up resistor such that the default configuration selects the fpga fabric tap. tck in 1 test clock serial input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/-down resistor. if jtag is not used, it is recommended to tie off tck to gnd or v jtag through a resistor placed close to the fpga pin. this prevents jtag operation in case tms enters an undesired state. note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. refer to table 5-1 on page 5-9 for more information. tdi in 1 test data serial input for jtag boundary scan, isp, and ujtag usage. there is an internal weak pull-up resistor on the tdi pin. tdo out 1 test data serial output for jtag boundary scan, isp, and ujtag usage. tms high test mode select the tms pin controls the use of the ieee1532 boundary scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trstb high boundary scan reset pin the trst pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an in ternal weak pull-up resistor on the trst pin. if jtag is not used, an external pul l-down resistor could be included to ensure the tap is held in reset mode. the resistor values must be chosen from table 5-1 on page 5-9 and must satisfy the pa rallel resistance value requirement. the values in table 5-1 on page 5-9 correspond to the resistor recommended when a single device is used. the values correspond to the equivalent parallel resistor when multiple devices are connected via a jtag chain. in critical applications, an upset in the jtag circuit could allow entering an undesired jtag state. in such cases, it is recommended that you tie off trst to gnd through a resistor placed close to the fpga pin. the trstb pin also resets the serial wire jtag ? debug port (swj-dp) circuitry within the cortex-m3.
smartfusion intelligent mixed signal fpgas revision 5 5-9 table 5-1 ? recommended tie-off values for the tck and trst pins v jtag tie-off resistance 1, 2 v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k notes: 1. the tck pin can be pulled up/down. 2. the trst pin can only be pulled down. 1. equivalent parallel resistance if more than one device is on jtag chain.
pin descriptions 5-10 revision 5 microcontroller subsystem (mss) name type polarity/ bus size description external memory controller emc_abx out 26 external memory controller address bus can also be used as an fpga user i/o (see "io" on page 5-5 ). emc_bytenx out low/2 external memory controller byte enable can also be used as an fpga user i/o (see "io" on page 5-5 ). emc_clk out rise external memory controller clock can also be used as an fpga user i/o (see "io" on page 5-5 ). emc_csx_n out low/2 external memo ry controller chip selects can also be used as an fpga user io (see "io" on page 5-5 ). emc_dbx in/out 16 external memory controller data bus can also be used as an fpga user i/o (see "io" on page 5-5 ). emc_oenx_n out low/2 external memory controller output enables can also be used as an fpga user io (see "io" on page 5-5 ). emc_rw_n out level external memory controlle r read/write. read = high, write = low. can also be used as an fpga user i/o (see "io" on page 5-5 ). inter-integrated circuit (i 2 c) peripherals i2c_0_scl in/out 1 i 2 c bus serial clock output. first i 2 c. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). i2c_0_sda in/out 1 i 2 c bus serial data input/output. first i 2 c. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). i2c_1_scl in/out 1 i 2 c bus serial clock output. second i 2 c. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). i2c_1_sda in/out 1 i 2 c bus serial data input/output. second i 2 c. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). serial peripheral inte rface (spi) controllers spi_0_clk out 1 clock. first spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). spi_0_di in 1 data input. first spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). spi_0_do out 1 data output. first spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). spi_0_ss out 1 slave select (chip select). first spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). spi_1_clk out 1 clock. second spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). spi_1_di in 1 data input. second spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ).
smartfusion intelligent mixed signal fpgas revision 5 5-11 spi_1_do out 1 data output. second spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). spi_1_ss out 1 slave select (c hip select). second spi. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). universal asynchronous receiver /transmitter (uart) peripherals uart_0_rxd in 1 receive data. first uart. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). uart_0_txd out 1 transmit data. first uart. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). uart_1_rxd in 1 receive data. second uart. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). uart_1_txd out 1 transmit data. second uart. can also be used as an mss gpio (see "gpio_x" on page 5-5 ). ethernet mac mac_clk in rise receive clock. 50 mhz 50 ppm clock source received from rmii phy. mac_crsdv in high carrier sense/receive data valid for rmii phy can also be used as an fpga user io (see "io" on page 5-5 ). mac_mdc out rise rmii management clock can also be used as an fpga user io (see "io" on page 5-5 ). mac_mdio in/out 1 rmii management data input/output can also be used as an fpga user io (see "io" on page 5-5 ). mac_rxdx in 2 ethernet mac receive data. da ta recovered and decoded by phy. the rxd[0] signal is the least significant bit. can also be used as an fpga user i/o (see "io" on page 5-5 ). mac_rxer in high ethernet mac re ceive error. if macrx_er is asserted during reception, the frame is received and status of the frame is updated with macrx_er. can also be used as an fpga user i/o (see "io" on page 5-5 ). mac_txdx out 2 ethernet mac transmit data. t he txd[0] signal is the least significant bit. can also be used as an fpga user i/o (see "io" on page 5-5 ). mac_txen out high ethernet mac transmit enable . when asserted, indicates valid data for the phy on the txd port. can also be used as an fpga user i/o (see "io" on page 5-5 ). name type polarity/ bus size description
pin descriptions 5-12 revision 5 analog front-end (afe) name type description associated with adc/sdd scb abps0 in scb 0 / active bipolar prescaler input 1. see the active bipolar pre scaler (abps) section in the smartfusion programmable analog user?s guide . adc0 scb0 abps1 in scb 0 / active bipola r prescaler input 2 adc0 scb0 abps2 in scb 1 / active bipola r prescaler input 1 adc0 scb1 abps3 in scb 1 / active bipola r prescaler input 2 adc0 scb1 abps4 in scb 2 / active bipola r prescaler input 1 adc1 scb2 abps5 in scb 2 / active bipola r prescaler input 2 adc1 scb2 abps6 in scb 3 / active bipola r prescaler input 1 adc1 scb3 abps7 in scb 3 / active bipolar prescaler input 2 adc1 scb3 abps8 in scb 4 / active bipolar prescaler input 1 adc2 scb4 abps9 in scb 4 / active bipolar prescaler input 2 adc2 scb4 adc0 in adc 0 direct input 0 / fpga input. see the "sigma-delta digital-to-analog converter (dac)" section in the smartfusion programmable analog user?s guide . adc0 scb0 adc1 in adc 0 direct input 1 / fpga input adc0 scb0 adc2 in adc 0 direct input 2 / fpga input adc0 scb1 adc3 in adc 0 direct input 3 / fpga input adc0 scb1 adc4 in adc 1 direct input 0 / fpga input adc1 scb2 adc5 in adc 1 direct input 1 / fpga input adc1 scb2 adc6 in adc 1 direct input 2 / fpga input adc1 scb3 adc7 in adc 1 direct input 3 / fpga input adc1 scb3 adc8 in adc 2 direct input 0 / fpga input adc2 scb4 adc9 in adc 2 direct input 1 / fpga input adc2 scb4 adc10 in adc 2 direct input 2 / fpga input adc2 n/a adc11 in adc 2 direct input 3 / fpga input adc2 n/a cm0 in scb 0 / high side of current monitor / comparator positive input. see the curr ent monitor section in the smartfusion programmable analog user?s guide . adc0 scb0 cm1 in scb 1 / high side of current monitor / comparator. positive input. adc0 scb1 cm2 in scb 2 / high side of current monitor / comparator. positive input. adc1 scb2 cm3 in scb 3 / high side of current monitor / comparator. positive input. adc1 scb3 cm4 in scb 4 / high side of current monitor / comparator. positive input. adc2 scb4 note: unused analog inputs should be grounded. this aids in shielding and prevents an undesired coupling path.
smartfusion intelligent mixed signal fpgas revision 5 5-13 tm0 in scb 0 / low side of current monitor / comparator negative input / high side of temperature monitor. see the temperature monitor section. adc0 scb0 tm1 in scb 1 / low side of current mo nitor / comparator. negative input / high side of temperature monitor. adc0 scb1 tm2 in scb 2 / low side of current mo nitor / comparator. negative input / high side of temperature monitor. adc1 scb2 tm3 in scb 3 low side of current monitor / comparator. negative input / high side of temperature monitor. adc1 scb3 tm4 in scb 4 low side of current monitor / comparator. negative input / high side of temperature monitor. adc2 scb4 sdd0 out output of sdd0 see the sigma-delta digital-to-analog converter (dac) section in the smartfusion programmable analog user?s guide . sdd0 n/a sdd1 out output of sdd1 sdd1 n/a sdd2 out output of sdd2 sdd2 n/a name type description associated with adc/sdd scb note: unused analog inputs should be grounded. this aids in shielding and prevents an undesired coupling path.
pin descriptions 5-14 revision 5 analog front-end pin-level function multiplexing table 5-2 describes the relationships between the various internal signals found in the analog front-end (afe) and how they are multiplexed onto the extern al package pins. note that, in general, only one function is available for those pads that have numer ous functions listed. the exclusion to this rule is when a comparator is used; the adc can still convert either input side of the comparator. table 5-2 ? relationships between signal s in the analog front-end pin adc channel dir.-in option prescaler current mon. temp. mon. compar. lvttl sdd mux sdd abps0 adc0_ch1 abps0_in abps1 adc0_ch2 abps1_in abps2 adc0_ch5 abps2_in abps3 adc0_ch6 abps3_in abps4 adc1_ch1 abps4_in abps5 adc1_ch2 abps5_in abps6 adc1_ch5 abps6_in abps7 adc1_ch6 abps7_in abps8 adc2_ch1 abps8_in abps9 adc2_ch2 abps9_in adc0 adc0_ch9 yes cmp1_p lvttl0_in adc1 adc0_ch10 yes cmp1_n lvttl1_in sddm0_out adc2 adc0_ch11 yes cmp3_p lvttl2_in adc3 adc0_ch12 yes cmp3_n lvttl3_in sddm1_out adc4 adc1_ch9 yes cmp5_p lvttl4_in adc5 adc1_ch10 yes cmp5_n lvttl5_in sddm2_out adc6 adc1_ch11 yes cmp7_p lvttl6_in adc7 adc1_ch12 yes cmp7_n lvttl7_in sddm3_out adc8 adc2_ch9 yes cmp9_p lvttl8_in adc9 adc2_ch10 yes cmp9_n lvttl9_in sddm4_out adc10 adc2_ch11 yes lvttl10_in adc11 adc2_ch12 yes lvttl11_in cm0 adc0_ch3 yes cm0_h cmp0_p cm1 adc0_ch7 yes cm1_h cmp2_p cm2 adc1_ch3 yes cm2_h cmp4_p cm3 adc1_ch7 yes cm3_h cmp6_p cm4 adc2_ch3 yes cm4_h cmp8_p sdd0 adc0_ch15 sdd0_out sdd1 adc1_ch15 sdd1_out notes: 1. abpsx_in: input to active bipolar prescaler channel x. 2. cmx_h/l: current monitor channel x, high/low side. 3. tmx_io: temperature monitor channel x. 4. cmpx_p/n: comparator channel x, positive/negative input. 5. lvttlx_in: lvttl i/o channel x. 6. sddmx_out: output from sigma-delta dac mux channel x. 7. sddx_out: direct output from sigma-delta dac channel x.
smartfusion intelligent mixed signal fpgas revision 5 5-15 sdd2 adc2_ch15 sdd2_out tm0 adc0_ch4 yes cm0_l tm0_io cmp0_n tm1 adc0_ch8 yes cm1_l tm1_io cmp2_n tm2 adc1_ch4 yes cm2_l tm2_io cmp4_n tm3 adc1_ch8 yes cm3_l tm3_io cmp6_n tm4 adc2_ch4 yes cm4_l tm4_io cmp8_n table 5-2 ? relationships between signal s in the analog front-end pin adc channel dir.-in option prescaler current mon. temp. mon. compar. lvttl sdd mux sdd notes: 1. abpsx_in: input to active bipolar prescaler channel x. 2. cmx_h/l: current monitor channel x, high/low side. 3. tmx_io: temperature monitor channel x. 4. cmpx_p/n: comparator channel x, positive/negative input. 5. lvttlx_in: lvttl i/o channel x. 6. sddmx_out: output from sigma-delta dac mux channel x. 7. sddx_out: direct output from sigma-delta dac channel x.
pin descriptions 5-16 revision 5 pin assignment tables 288-pin csp for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: bottom view 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa a1 ball pad corner
smartfusion intelligent mixed signal fpgas revision 5 5-17 pin number 288-pin csp a2f200 function a2f500 function a1 vccfpgaiob0 vccfpgaiob0 a2 gndq gndq a3 emc_clk/gaa0/io00ndb0v0 emc_clk/gaa0/io02ndb0v0 a4 emc_rw_n/gaa1/io00pdb0v0 emc_rw_n/gaa1/io02pdb0v0 a5 gnd gnd a6 emc_cs1_n/gab1/io01pdb0v0 emc_cs1_n/g ab1/io05pdb0v0 a7 emc_cs0_n/gab0/io01ndb0v0 emc_cs0_n/gab0/io05ndb0v0 a8 emc_ab[0]/io04npb0v0 emc_ab[0]/io06npb0v0 a9 vccfpgaiob0 vccfpgaiob0 a10 emc_ab[4]/io06ndb0v0 emc_ab[4]/io10ndb0v0 a11 emc_ab[8]/io08npb0v0 emc_ab[8]/io13npb0v0 a12 emc_ab[14]/io11npb0v0 emc_ab[14]/io15npb0v0 a13 gnd gnd a14 emc_ab[18]/io13ndb0v0 emc_ab[18]/io18ndb0v0 a15 emc_ab[24]/io16ndb0v0 emc_ab[24]/io20ndb0v0 a16 emc_ab[25]/io16pdb0v0 emc_ab[25]/io20pdb0v0 a17 vccfpgaiob0 vccfpgaiob0 a18 emc_ab[20]/io14ndb0v0 emc_ab[20]/io21ndb0v0 a19 emc_ab[21]/io14pdb0v0 emc_ab[21]/io21pdb0v0 a20 gndq gndq a21 gnd gnd aa1 abps1 abps1 aa2 gndaq gndaq aa3 gnda gnda aa4 vcc33n vcc33n aa5 sdd0 sdd0 aa6 abps0 abps0 aa7 gndtm0 gndtm0 aa8 abps2 abps2 aa9 varef0 varef0 aa10 gnd15adc0 gnd15adc0 aa11 adc6 adc6 aa12 abps7 abps7 aa13 tm2 tm2 aa14 abps4 abps4 aa15 sdd1 sdd1 note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-18 revision 5 aa16 gndvaref gndvaref aa17 varefout varefout aa18 pu_n pu_n aa19 vcc33a vcc33a aa20 ptem ptem aa21 gnd gnd b1 gnd gnd b21 gbb2/io20ndb1v0 gbb2/io27ndb1v0 c1 emc_db[15]/gaa2/io71pdb5v0 emc_db[15]/gaa2/io88pdb5v0 c3 vcompla vcompla0 c4 vccpll vccpll0 c5 vccfpgaiob0 vccfpgaiob0 c6 emc_ab[1]/io04ppb0v0 emc_ab[1]/io06ppb0v0 c7 gnd gnd c8 emc_oen0_n/io03ndb0v0 emc_oen0_n/io08ndb0v0 c9 emc_ab[2]/io05ndb0v0 emc_ab[2]/io09ndb0v0 c10 emc_ab[5]/io06pdb0v0 emc_ab[5]/io10pdb0v0 c11 vccfpgaiob0 vccfpgaiob0 c12 emc_ab[9]/io08ppb0v0 emc_ab[9]/io13ppb0v0 c13 emc_ab[15]/io11ppb0v0 emc_ab[15]/io15ppb0v0 c14 emc_ab[19]/io13pdb0v0 emc_ab[19]/io18pdb0v0 c15 gnd gnd c16 emc_ab[22]/io15ndb0v0 emc_ab[22]/io19ndb0v0 c17 emc_ab[23]/io15pdb0v0 emc_ab[23]/io19pdb0v0 c18 nc vccpll1 c19 nc vcompla1 c21 gba2/io20pdb1v0 gba2/io27pdb1v0 d1 emc_db[14]/gab2/io71ndb5v0 emc_db[14]/gab2/io88ndb5v0 d3 vccfpgaiob5 vccfpgaiob5 d19 gnd gnd d21 vccfpgaiob1 vccfpgaiob1 e1 emc_db[13]/gac2/io70pdb5v0 emc_db[13]/gac2/io87pdb5v0 e3 emc_db[12]/io70ndb5v0 emc_db[12]/io87ndb5v0 e5 gndq gndq e6 emc_byten[0]/gac0/io02ndb0v0 emc_byten[0]/g ac0/io07ndb0v0 e7 emc_byten[1]/gac1/io02pdb0v0 emc_byten[1]/gac1/io07pdb0v0 pin number 288-pin csp a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-19 e8 emc_oen1_n/io03pdb0v0 emc_oen1_n/io08pdb0v0 e9 emc_ab[3]/io05pdb0v0 emc_ab[3]/io09pdb0v0 e10 emc_ab[10]/io09ndb0v0 emc_ab[10]/io11ndb0v0 e11 emc_ab[7]/io07pdb0v0 emc_ab[7]/io12pdb0v0 e12 emc_ab[13]/io10pdb0v0 emc_ab[13]/io14pdb0v0 e13 emc_ab[16]/io12ndb0v0 emc_ab[16]/io17ndb0v0 e14 emc_ab[17]/io12pdb0v0 emc_ab[17]/io17pdb0v0 e15 gcb0/io27ndb1v0 gcb0/io34ndb1v0 e16 gcb1/io27pdb1v0 gcb1/io34pdb1v0 e17 gcb2/io24pdb1v0 gcb2/io33pdb1v0 e19 gca0/io28ndb1v0 gca0/io36ndb1v0 e21 gca1/io28pdb1v0 gca1/io36pdb1v0 f1 vccfpgaiob5 vccfpgaiob5 f3 gfb2/io68ndb5v0 gfb2/io85ndb5v0 f5 gfa2/io68pdb5v0 gfa2/io85pdb5v0 f6 emc_db[11]/io69pdb5v0 emc_db[11]/io86pdb5v0 f7 gnd gnd f8 gfc1/io66ppb5v0 gfc1/io83ppb5v0 f9 vccfpgaiob0 vccfpgaiob0 f10 emc_ab[11]/io09pdb0v0 emc_ab[11]/io11pdb0v0 f11 emc_ab[6]/io07ndb0v0 emc_ab[6]/io12ndb0v0 f12 emc_ab[12]/io10ndb0v0 emc_ab[12]/io14ndb0v0 f13 gnd gnd f14 gcc1/io26ppb1v0 gcc1/io35ppb1v0 f15 gndq gndq f16 vccfpgaiob1 vccfpgaiob1 f17 io24ndb1v0 io33ndb1v0 f19 gdb1/io30pdb1v0 gdb1/io39pdb1v0 f21 gdb0/io30ndb1v0 gdb0/io39ndb1v0 g1 io67ndb5v0 io84ndb5v0 g3 gfc2/io67pdb5v0 gfc2/io84pdb5v0 g5 gfb1/io65pdb5v0 gfb1/io82pdb5v0 g6 emc_db[10]/io69ndb5v0 emc_db[10]/io86ndb5v0 g9 gfc0/io66npb5v0 gfc0/io83npb5v0 g13 gcc0/io26npb1v0 gcc0/io35npb1v0 g16 gda0/io31ndb1v0 gda0/io40ndb1v0 pin number 288-pin csp a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-20 revision 5 g17 gdc1/io29pdb1v0 gdc1/io38pdb1v0 g19 gdc0/io29ndb1v0 gdc0/io38ndb1v0 g21 gnd gnd h1 emc_db[9]/gec1/io63ppb5v0 emc_db[9]/gec 1/io80ppb5v0 h3 gnd gnd h5 gfb0/io65ndb5v0 gfb0/io82ndb5v0 h6 emc_db[7]/geb1/io62pdb5v0 emc_db[7]/geb1/io79pdb5v0 h8 gnd gnd h9 vcc vcc h10 gnd gnd h11 vcc vcc h12 gnd gnd h13 vcc vcc h14 gnd gnd h16 gda1/io31pdb1v0 gda1/io40pdb1v0 h17 gdc2/io32ppb1v0 gdc2/io41ppb1v0 h19 vccfpgaiob1 vccfpgaiob1 h21 gdb2/io33pdb1v0 gdb2/io42pdb1v0 j1 emc_db[4]/gea0/io61npb5v0 emc_db[4]/gea0/io78npb5v0 j3 emc_db[8]/gec0/io63npb5v0 emc_db[8]/gec 0/io80npb5v0 j5 emc_db[1]/geb2/io59pdb5v0 emc_db[1]/geb2/io76pdb5v0 j6 emc_db[6]/geb0/io62ndb5v0 emc_db[6]/geb0/io79ndb5v0 j7 vccfpgaiob5 vccfpgaiob5 j8 vcc vcc j9 gnd gnd j10 vcc vcc j11 gnd gnd j12 vcc vcc j13 gnd gnd j14 vcc vcc j15 vpp vpp j16 io32npb1v0 io41npb1v0 j17 gndq gndq j19 vccmainxtal vccmainxtal j21 gda2/io33ndb1v0 gda2/io42ndb1v0 k1 gnd gnd pin number 288-pin csp a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-21 k3 emc_db[5]/gea1/io61ppb5v0 emc_db[5]/g ea1/io78ppb5v0 k5 emc_db[0]/gea2/io59ndb5v0 emc_db[0]/gea2/io76ndb5v0 k6 emc_db[3]/gec2/io60ppb5v0 emc_db[3]/gec 2/io77ppb5v0 k8 gnd gnd k9 vcc vcc k10 gnd gnd k11 vcc vcc k12 gnd gnd k13 vcc vcc k14 gnd gnd k16 lpxout lpxout k17 gndlpxtal gndlpxtal k19 gndmainxtal gndmainxtal k21 mainxin mainxin l1 gndrcosc gndrcosc l3 vccfpgaiob5 vccfpgaiob5 l5 emc_db[2]/io60npb5v0 emc_db[2]/io77npb5v0 l6 gndq gndq l8 vcc vcc l9 gnd gnd l10 vcc vcc l12 vcc vcc l13 gnd gnd l14 vcc vcc l16 vcclpxtal vcclpxtal l17 vddbat vddbat l19 lpxin lpxin l21 mainxout mainxout m1 vccrcosc vccrcosc m3 mss_reset_n mss_reset_n m5 gpio_5/io42rsb4v0 gpio_5/io51rsb4v0 m6 gnd gnd m8 gnd gnd m9 vcc vcc m10 gnd gnd m11 vcc vcc pin number 288-pin csp a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-22 revision 5 m12 gnd gnd m13 vcc vcc m14 gnd gnd m16 tms tms m17 vjtag vjtag m19 tdo tdo m21 trstb trstb n1 vccmssiob4 vccmssiob4 n3 gnd gnd n5 gpio_4/io43rsb4v0 gpio_4/io52rsb4v0 n6 gpio_8/io39rsb4v0 gpio_8/io48rsb4v0 n7 gpio_9/io38rsb4v0 gpio_9/io47rsb4v0 n8 vcc vcc n9 gnd gnd n10 vcc vcc n11 gnd gnd n12 vcc vcc n13 gnd gnd n14 vcc vcc n15 gnd gnd n16 tck tck n17 tdi tdi n19 gndenvm gndenvm n21 vccenvm vccenvm p1 mac_mdc/io48rsb4v0 mac_mdc/io57rsb4v0 p3 gpio_7/io40rsb4v0 gpio_7/io49rsb4v0 p5 gpio_6/io41rsb4v0 gpio_6/io50rsb4v0 p6 vccmssiob4 vccmssiob4 p8 gnd gnd p9 vcc vcc p10 gnd gnd p11 vcc vcc p12 gnd gnd p13 vcc vcc p14 gnd gnd p16 jtagsel jtagsel pin number 288-pin csp a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-23 p17 i2c_0_scl/gpio_23 i2c_0_scl/gpio_23 p19 vccmssiob2 vccmssiob2 p21 gnd gnd r1 mac_mdio/io49rsb4v0 mac_mdio/io58rsb4v0 r3 mac_txen/io52rsb4v0 mac_txen/io61rsb4v0 r5 mac_txd[0] /io56rsb4v0 mac_txd[0]/io65rsb4v0 r6 mac_crsdv/io51rsb4v0 mac_crsdv/io60rsb4v0 r9 gnda gnda r13 gnda gnda r16 uart_1_rxd/gpio_29 uart_1_rxd/gpio_29 r17 uart_1_txd/gpio_28 uart_1_txd/gpio_28 r19 i2c_0_sda/gpio_22 i2c_0_sda/gpio_22 r21 i2c_1_sda/gpio_30 i2c_1_sda/gpio_30 t1 gnd gnd t3 mac_txd[1] /io55rsb4v0 mac_txd[1]/io64rsb4v0 t5 mac_rxd[1]/io53rsb4v0 mac_rxd[1]/io62rsb4v0 t6 mac_rxer/io50rsb4v0 mac_rxer/io59rsb4v0 t7 cm1 cm1 t8 adc1 adc1 t9 gnd33adc0 gnd33adc0 t10 vcc15adc0 vcc15adc0 t11 gnd33adc1 gnd33adc1 t12 varef1 varef1 t13 adc4 adc4 t14 tm3 tm3 t15 spi_1_ss/gpio_27 spi_1_ss/gpio_27 t16 vccmssiob2 vccmssiob2 t17 uart_0_rxd/gpio_21 uart_0_rxd/gpio_21 t19 uart_0_txd/gpio_20 uart_0_txd/gpio_20 t21 i2c_1_scl/gpio_31 i2c_1_scl/gpio_31 u1 mac_rxd[0]/io54rsb4v0 mac_rxd[0]/io63rsb4v0 u3 vccmssiob4 vccmssiob4 u5 vcc33sdd0 vcc33sdd0 u6 vcc15a vcc15a u7 abps3 abps3 u8 adc2 adc2 pin number 288-pin csp a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-24 revision 5 u9 vcc33adc0 vcc33adc0 u10 gnd15adc1 gnd15adc1 u11 vcc33adc1 vcc33adc1 u12 adc7 adc7 u13 abps6 abps6 u14 gndtm1 gndtm1 u15 spi_1_clk/gpio_ 26 spi_1_clk/gpio_26 u16 spi_0_clk/gpio_ 18 spi_0_clk/gpio_18 u17 spi_0_ss/gpio_19 spi_0_ss/gpio_19 u19 gnd gnd u21 spi_1_do/gpio_24 spi_1_do/gpio_24 v1 mac_clk mac_clk v3 gndsdd0 gndsdd0 v19 spi_1_di/gpio_ 25 spi_1_di/gpio_25 v21 vccmssiob2 vccmssiob2 w1 pcap pcap w3 ncap ncap w4 cm0 cm0 w5 tm0 tm0 w6 tm1 tm1 w7 adc0 adc0 w8 adc3 adc3 w9 gnd33adc0 gnd33adc0 w10 vcc15adc1 vcc15adc1 w11 gnd33adc1 gnd33adc1 w12 adc5 adc5 w13 cm3 cm3 w14 cm2 cm2 w15 abps5 abps5 w16 gndaq gndaq w17 vcc33sdd1 vcc33sdd1 w18 gndsdd1 gndsdd1 w19 ptbase ptbase w21 spi_0_di/gpio_17 spi_0_di/gpio_17 y1 vcc33ap vcc33ap y21 spi_0_do/gpio_16 spi_0_do/gpio_16 pin number 288-pin csp a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-25 pin number 288-pin csp a2f060 function a2f200 function a1 vccfpgaiob0 vccfpgaiob0 a2 gndq gndq a3 emc_clk/gaa0/io00ndb0v 0 emc_clk/gaa0/io00ndb0v0 a4 emc_rw_n/gaa1/io00pdb0v0 emc_rw_n/gaa1/io00pdb0v0 a5 gnd gnd a6 emc_cs1_n/gab1/io01pdb0v 0 emc_cs1_n/gab1/io01pdb0v0 a7 emc_cs0_n/gab0/io01ndb0v0 e mc_cs0_n/gab0/io01ndb0v0 a8 emc_ab[0]/io04npb0v0 emc_ab[0]/io04npb0v0 a9 vccfpgaiob0 vccfpgaiob0 a10 emc_ab[4]/io06ndb0v0 emc_ab[4]/io06ndb0v0 a11 emc_ab[8]/io08npb0 v0 emc_ab[8]/io08npb0v0 a12 emc_ab[14]/io11npb0v 0 emc_ab[14]/io11npb0v0 a13 gnd gnd a14 emc_ab[18]/io13ndb0v0 emc_ab[18]/io13ndb0v0 a15 emc_ab[24]/io16ndb0v0 emc_ab[24]/io16ndb0v0 a16 emc_ab[25]/io16pdb0 v0 emc_ab[25]/io16pdb0v0 a17 vccfpgaiob0 vccfpgaiob0 a18 emc_ab[20]/io14ndb0v0 emc_ab[20]/io14ndb0v0 a19 emc_ab[21]/io14pdb0 v0 emc_ab[21]/io14pdb0v0 a20 gndq gndq a21 gnd gnd aa1 nc abps1 aa2 gndaq gndaq aa3 gnda gnda aa4 vcc33n vcc33n aa5 sdd0 sdd0 aa6 nc abps0 aa7 nc gndtm0 aa8 nc abps2 aa9 nc varef0 aa10 nc gnd15adc0 aa11 adc6 adc6 aa12 abps7 abps7 aa13 tm2 (adc) tm2 aa14 nc abps4 aa15 nc sdd1 note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-26 revision 5 aa16 gndvaref gndvaref aa17 varefout varefout aa18 pu_n pu_n aa19 vcc33a vcc33a aa20 ptem ptem aa21 gnd gnd b1 gnd gnd b21 gbb2/io20ndb1v0 gbb2/io20ndb1v0 c1 emc_db[15]/gaa2/io71pdb5v0 emc_db[15]/gaa2/io71pdb5v0 c3 vcompla vcompla c4 vccpll vccpll c5 vccfpgaiob0 vccfpgaiob0 c6 emc_ab[1]/io04ppb0v0 emc_ab[1]/io04ppb0v0 c7 gnd gnd c8 emc_oen0_n/io03ndb0v0 emc_oen0_n/io03ndb0v0 c9 emc_ab[2]/io05ndb0v0 emc_ab[2]/io05ndb0v0 c10 emc_ab[5]/io06pdb0v 0 emc_ab[5]/io06pdb0v0 c11 vccfpgaiob0 vccfpgaiob0 c12 emc_ab[9]/io08ppb0 v0 emc_ab[9]/io08ppb0v0 c13 emc_ab[15]/io11ppb0 v0 emc_ab[15]/io11ppb0v0 c14 emc_ab[19]/io13pdb0 v0 emc_ab[19]/io13pdb0v0 c15 gnd gnd c16 emc_ab[22]/io15ndb0v0 emc_ab[22]/io15ndb0v0 c17 emc_ab[23]/io15pdb0 v0 emc_ab[23]/io15pdb0v0 c18 nc nc c19 nc nc c21 gba2/io20pdb1v0 gba2/io20pdb1v0 d1 emc_db[14]/gab2/io71ndb5v0 e mc_db[14]/gab2/io71ndb5v0 d3 vccfpgaiob5 vccfpgaiob5 d19 gnd gnd d21 vccfpgaiob1 vccfpgaiob1 e1 emc_db[13]/gac2 /io70pdb5v0 emc_db[13]/gac2/io70pdb5v0 e3 emc_db[12]/io70ndb5v 0 emc_db[12]/io70ndb5v0 e5 gndq gndq e6 emc_byten[0]/gac0/io02ndb0v0 e mc_byten[0]/gac0/io02ndb0v0 e7 emc_byten[1]/gac1/io 02pdb0v0 emc_byten[1 ]/gac1/io02pdb0v0 pin number 288-pin csp a2f060 function a2f200 function note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-27 e8 emc_oen1_n/io03pdb0v0 emc_oen1_n/io03pdb0v0 e9 emc_ab[3]/io05pdb0v 0 emc_ab[3]/io05pdb0v0 e10 emc_ab[10]/io09ndb0v0 emc_ab[10]/io09ndb0v0 e11 emc_ab[7]/io07pdb0v 0 emc_ab[7]/io07pdb0v0 e12 emc_ab[13]/io10pdb0 v0 emc_ab[13]/io10pdb0v0 e13 emc_ab[16]/io12ndb0v0 emc_ab[16]/io12ndb0v0 e14 emc_ab[17]/io12pdb0 v0 emc_ab[17]/io12pdb0v0 e15 gcb0/io27ndb1v0 gcb0/io27ndb1v0 e16 gcb1/io27pdb1v0 gcb1/io27pdb1v0 e17 gcb2/io24pdb1v0 gcb2/io24pdb1v0 e19 gca0/io28ndb1v0 gca0/io28ndb1v0 e21 gca1/io28pdb1v0 gca1/io28pdb1v0 f1 vccfpgaiob5 vccfpgaiob5 f3 gfb2/io68ndb5v0 gfb2/io68ndb5v0 f5 gfa2/io68pdb5v0 gfa2/io68pdb5v0 f6 emc_db[11]/io69pdb5v 0 emc_db[11]/io69pdb5v0 f7 gnd gnd f8 nc gfc1/io66ppb5v0 f9 vccfpgaiob0 vccfpgaiob0 f10 emc_ab[11]/io09pdb0v 0 emc_ab[11]/io09pdb0v0 f11 emc_ab[6]/io07ndb0v0 emc_ab[6]/io07ndb0v0 f12 emc_ab[12]/io10ndb0v0 emc_ab[12]/io10ndb0v0 f13 gnd gnd f14 gcc1/io26ppb1v0 gcc1/io26ppb1v0 f15 gndq gndq f16 vccfpgaiob1 vccfpgaiob1 f17 io24ndb1v0 io24ndb1v0 f19 gdb1/io30pdb1v0 gdb1/io30pdb1v0 f21 gdb0/io30ndb1v0 gdb0/io30ndb1v0 g1 io67ndb5v0 io67ndb5v0 g3 gfc2/io67pdb5v0 gfc2/io67pdb5v0 g5 nc gfb1/io65pdb5v0 g6 emc_db[10]/io69ndb5v 0 emc_db[10]/io69ndb5v0 g9 nc gfc0/io66npb5v0 g13 gcc0/io26npb1v0 gcc0/io26npb1v0 g16 nc gda0/io31ndb1v0 pin number 288-pin csp a2f060 function a2f200 function note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-28 revision 5 g17 gdc1/io29pdb1v0 gdc1/io29pdb1v0 g19 gdc0/io29ndb1v0 gdc0/io29ndb1v0 g21 gnd gnd h1 emc_db[9]/gec1/io63ppb5 v0 emc_db[9]/g ec1/io63ppb5v0 h3 gnd gnd h5 nc gfb0/io65ndb5v0 h6 emc_db[7]/geb1/io62pdb5v 0 emc_db[7]/geb1/io62pdb5v0 h8 gnd gnd h9 vcc vcc h10 gnd gnd h11 vcc vcc h12 gnd gnd h13 vcc vcc h14 gnd gnd h16 nc gda1/io31pdb1v0 h17 nc gdc2/io32ppb1v0 h19 vccfpgaiob1 vccfpgaiob1 h21 nc gdb2/io33pdb1v0 j1 emc_db[4]/gea0/io61npb5 v0 emc_db[4]/gea0/io61npb5v0 j3 emc_db[8]/gec0/io63npb5v0 emc_db[8]/gec0/io63npb5v0 j5 emc_db[1]/geb2/io59pdb5v 0 emc_db[1]/geb2/io59pdb5v0 j6 emc_db[6]/geb0/io62ndb5v0 emc_db[6]/geb0/io62ndb5v0 j7 vccfpgaiob5 vccfpgaiob5 j8 vcc vcc j9 gnd gnd j10 vcc vcc j11 gnd gnd j12 vcc vcc j13 gnd gnd j14 vcc vcc j15 vpp vpp j16 nc io32npb1v0 j17 gndq gndq j19 vccmainxtal vccmainxtal j21 nc gda2/io33ndb1v0 k1 gnd gnd pin number 288-pin csp a2f060 function a2f200 function note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-29 k3 emc_db[5]/gea1/io61ppb5 v0 emc_db[5]/gea1/io61ppb5v0 k5 emc_db[0]/gea2/io59ndb5v 0 emc_db[0]/gea2/io59ndb5v0 k6 emc_db[3]/gec2/io60ppb5 v0 emc_db[3]/g ec2/io60ppb5v0 k8 gnd gnd k9 vcc vcc k10 gnd gnd k11 vcc vcc k12 gnd gnd k13 vcc vcc k14 gnd gnd k16 lpxout lpxout k17 gndlpxtal gndlpxtal k19 gndmainxtal gndmainxtal k21 mainxin mainxin l1 gndrcosc gndrcosc l3 vccfpgaiob5 vccfpgaiob5 l5 emc_db[2]/io60npb5v0 emc_db[2]/io60npb5v0 l6 gndq gndq l8 vcc vcc l9 gnd gnd l10 vcc vcc l12 vcc vcc l13 gnd gnd l14 vcc vcc l16 vcclpxtal vcclpxtal l17 vddbat vddbat l19 lpxin lpxin l21 mainxout mainxout m1 vccrcosc vccrcosc m3 mss_reset_n mss_reset_n m5 gpio_5/io42rsb4v0 gpio_5/io42rsb4v0 m6 gnd gnd m8 gnd gnd m9 vcc vcc m10 gnd gnd m11 vcc vcc pin number 288-pin csp a2f060 function a2f200 function note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-30 revision 5 m12 gnd gnd m13 vcc vcc m14 gnd gnd m16 tms tms m17 vjtag vjtag m19 tdo tdo m21 trstb trstb n1 vccmssiob4 vccmssiob4 n3 gnd gnd n5 gpio_4/io43rsb4v0 gpio_4/io43rsb4v0 n6 gpio_8/io39rsb4v0 gpio_8/io39rsb4v0 n7 gpio_9/io38rsb4v0 gpio_9/io38rsb4v0 n8 vcc vcc n9 gnd gnd n10 vcc vcc n11 gnd gnd n12 vcc vcc n13 gnd gnd n14 vcc vcc n15 gnd gnd n16 tck tck n17 tdi tdi n19 gndenvm gndenvm n21 vccenvm vccenvm p1 io48rsb4v0 mac_mdc/io48rsb4v0 p3 gpio_7/io40rsb4v0 gpio_7/io40rsb4v0 p5 gpio_6/io41rsb4v0 gpio_6/io41rsb4v0 p6 vccmssiob4 vccmssiob4 p8 gnd gnd p9 vcc vcc p10 gnd gnd p11 vcc vcc p12 gnd gnd p13 vcc vcc p14 gnd gnd p16 jtagsel jtagsel pin number 288-pin csp a2f060 function a2f200 function note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-31 p17 i2c_0_scl/gpio_23 i2c_0_scl/gpio_23 p19 vccmssiob2 vccmssiob2 p21 gnd gnd r1 io49rsb4v0 mac_mdio/io49rsb4v0 r3 io52rsb4v0 mac_txen/io52rsb4v0 r5 io56rsb4v0 mac_txd[0]/io56rsb4v0 r6 io51rsb4v0 mac_crsdv/io51rsb4v0 r9 gnda gnda r13 gnda gnda r16 uart_1_rxd/gpio_29 uart_1_rxd/gpio_29 r17 uart_1_txd/gpio_28 uart_1_txd/gpio_28 r19 i2c_0_sda/gpio_22 i2c_0_sda/gpio_22 r21 i2c_1_sda/gpio_30 i2c_1_sda/gpio_30 t1 gnd gnd t3 nc mac_txd[1]/io55rsb4v0 t5 nc mac_rxd[1]/io53rsb4v0 t6 io50rsb4v0 mac_rxer/io50rsb4v0 t7 nc cm1 t8 nc adc1 t9 nc gnd33adc0 t10 nc vcc15adc0 t11 gnd33adc1 gnd33adc1 t12 varef1 varef1 t13 adc4 adc4 t14 tm3 tm3 t15 spi_1_ss/gpio_27 spi_1_ss/gpio_27 t16 vccmssiob2 vccmssiob2 t17 uart_0_rxd/gpio_21 uart_0_rxd/gpio_21 t19 uart_0_txd/gpio_20 uart_0_txd/gpio_20 t21 i2c_1_scl/gpio_31 i2c_1_scl/gpio_31 u1 nc mac_rxd[0]/io54rsb4v0 u3 vccmssiob4 vccmssiob4 u5 vcc33sdd0 vcc33sdd0 u6 vcc15a vcc15a u7 nc abps3 u8 nc adc2 pin number 288-pin csp a2f060 function a2f200 function note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-32 revision 5 u9 nc vcc33adc0 u10 gnd15adc1 gnd15adc1 u11 vcc33adc1 vcc33adc1 u12 adc7 adc7 u13 abps6 abps6 u14 gndtm1 gndtm1 u15 spi_1_clk/gpio_26 spi_1_clk/gpio_26 u16 spi_0_clk/gpio_18 spi_0_clk/gpio_18 u17 spi_0_ss/gpio_19 spi_0_ss/gpio_19 u19 gnd gnd u21 spi_1_do/gpio_24 spi_1_do/gpio_24 v1 nc mac_clk v3 gndsdd0 gndsdd0 v19 spi_1_di/gpio _25 spi_1_di/gpio_25 v21 vccmssiob2 vccmssiob2 w1 pcap pcap w3 ncap ncap w4 nc cm0 w5 nc tm0 w6 nc tm1 w7 nc adc0 w8 nc adc3 w9 nc gnd33adc0 w10 vcc15adc1 vcc15adc1 w11 gnd33adc1 gnd33adc1 w12 adc5 adc5 w13 cm3 cm3 w14 cm2 (adc) cm2 w15 nc abps5 w16 gndaq gndaq w17 nc vcc33sdd1 w18 nc gndsdd1 w19 ptbase ptbase w21 spi_0_di/gpio_17 spi_0_di/gpio_17 y1 vcc33ap vcc33ap y21 spi_0_do/gpio_16 spi_0_do/gpio_16 pin number 288-pin csp a2f060 function a2f200 function note: shading denotes pins that do not have completely id entical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-33 256-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . . 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
pin descriptions 5-34 revision 5 pin number 256-pin fbga a2f200 function a2f500 function a1 gnd gnd a2 vccfpgaiob0 vccfpgaiob0 a3 emc_ab[0]/io04ndb0v0 emc_ab[0]/io06ndb0v0 a4 emc_ab[1]/io04pdb0v0 emc_ab[1]/io06pdb0v0 a5 gnd gnd a6 emc_ab[3]/io05pdb0v0 emc_ab[3]/io09pdb0v0 a7 emc_ab[5]/io06pdb0v0 emc_ab[5]/io10pdb0v0 a8 vccfpgaiob0 vccfpgaiob0 a9 gnd gnd a10 emc_ab[14]/io11ndb0v0 emc_ab[14]/io15ndb0v0 a11 emc_ab[15]/io11pdb0v0 emc_ab[15]/io15pdb0v0 a12 gnd gnd a13 emc_ab[20]/io14ndb0v0 emc_ab[20]/io21ndb0v0 a14 emc_ab[24]/io16ndb0v0 emc_ab[24]/io20ndb0v0 a15 vccfpgaiob0 vccfpgaiob0 a16 gnd gnd b1 emc_db[15]/gaa2/io71pdb5v0 emc_db[15]/gaa2/io88pdb5v0 b2 gnd gnd b3 emc_byten[1]/ga c1/io02pdb0v0 emc_byten[1]/gac1/io07pdb0v0 b4 emc_oen0_n/io03ndb0v0 emc_oen0_n/io08ndb0v0 b5 emc_oen1_n/io03pdb0v0 emc_oen1_n/io08pdb0v0 b6 emc_ab[2]/io05ndb0v0 emc_ab[2]/io09ndb0v0 b7 emc_ab[4]/io06ndb0v0 emc_ab[4]/io10ndb0v0 b8 emc_ab[9]/io08pdb0v0 emc_ab[9]/io13pdb0v0 b9 emc_ab[12]/io10ndb0v0 emc_ab[12]/io14ndb0v0 b10 emc_ab[13]/io10pdb0v0 emc_ab[13]/io14pdb0v0 b11 emc_ab[16]/io12ndb0v0 emc_ab[16]/io17ndb0v0 b12 emc_ab[18]/io13ndb0v0 emc_ab[18]/io18ndb0v0 b13 emc_ab[21]/io14pdb0v0 emc_ab[21]/io21pdb0v0 b14 emc_ab[25]/io16pdb0v0 emc_ab[25]/io20pdb0v0 b15 gnd gnd b16 gndq gndq c1 emc_db[14]/gab2/io71ndb5v0 emc_db[14]/gab2/io88ndb5v0 note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-35 c2 vccpll vccpll0 c3 emc_byten[0]/g ac0/io02ndb0v0 emc_byten[0]/gac0/io07ndb0v0 c4 vccfpgaiob0 vccfpgaiob0 c5 emc_cs0_n/gab0/io01ndb0v0 emc_cs0_n/gab0/io05ndb0v0 c6 emc_cs1_n/gab1/io01pdb0v0 emc_cs1_n/gab1/io05pdb0v0 c7 gnd gnd c8 emc_ab[8]/io08ndb0v0 emc_ab[8]/io13ndb0v0 c9 emc_ab[11]/io09pdb0v0 emc_ab[11]/io11pdb0v0 c10 vccfpgaiob0 vccfpgaiob0 c11 emc_ab[17]/io12pdb0v0 emc_ab[17]/io17pdb0v0 c12 emc_ab[19]/io13pdb0v0 emc_ab[19]/io18pdb0v0 c13 gnd gnd c14 gba2/io20ppb1v0 gba2/io27ppb1v0 c15 gca2/io23pdb1v0 gca2/io28pdb1v0 c16 io23ndb1v0 io28ndb1v0 d1 vccfpgaiob5 vccfpgaiob5 d2 vcompla vcompla0 d3 gnd gnd d4 gndq gndq d5 emc_clk/gaa0/io00ndb0v0 emc_clk/gaa0/io02ndb0v0 d6 emc_rw_n/gaa1/io00pdb0v0 emc_rw_n/gaa1/io02pdb0v0 d7 emc_ab[6]/io07ndb0v0 emc_ab[6]/io12ndb0v0 d8 emc_ab[7]/io07pdb0v0 emc_ab[7]/io12pdb0v0 d9 emc_ab[10]/io09ndb0v0 emc_ab[10]/io11ndb0v0 d10 emc_ab[22]/io15ndb0v0 emc_ab[22]/io19ndb0v0 d11 emc_ab[23]/io15pdb0v0 emc_ab[23]/io19pdb0v0 d12 gndq gndq d13 gbb2/io20npb1v0 gbb2/io27npb1v0 d14 gcb2/io24pdb1v0 gcb2/io33pdb1v0 d15 io24ndb1v0 io33ndb1v0 d16 vccfpgaiob1 vccfpgaiob1 e1 emc_db[13]/gac2/io70pdb5v0 emc_db[13]/gac2/io87pdb5v0 e2 emc_db[12]/io70ndb5v0 emc_db[12]/io87ndb5v0 pin number 256-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
pin descriptions 5-36 revision 5 e3 gfa2/io68pdb5v0 gfa2/io85pdb5v0 e4 emc_db[10]/io69npb5v0 emc_db[10]/io86npb5v0 e5 gndq gndq e6 gnd gnd e7 vccfpgaiob0 vccfpgaiob0 e8 gnd gnd e9 vccfpgaiob0 vccfpgaiob0 e10 gnd gnd e11 vccfpgaiob0 vccfpgaiob0 e12 gca1/io28pdb1v0 gca1/io36pdb1v0 e13 vccfpgaiob1 vccfpgaiob1 e14 gcb1/io27pdb1v0 gcb1/io34pdb1v0 e15 gdc1/io29pdb1v0 gdc1/io38pdb1v0 e16 gdc0/io29ndb1v0 gdc0/io38ndb1v0 f1 emc_db[9]/gec 1/io63pdb5v0 emc_db[9]/gec1/io80pdb5v0 f2 gnd gnd f3 gfb2/io68ndb5v0 gfb2/io85ndb5v0 f4 vccfpgaiob5 vccfpgaiob5 f5 emc_db[11]/io69ppb5v0 emc_db[11]/io86ppb5v0 f6 vccfpgaiob5 vccfpgaiob5 f7 gnd gnd f8 vcc vcc f9 gnd gnd f10 vcc vcc f11 gnd gnd f12 gca0/io28ndb1v0 gca0/io36ndb1v0 f13 gndq gndq f14 gcb0/io27ndb1v0 gcb0/io34ndb1v0 f15 gnd gnd f16 vccenvm vccenvm g1 emc_db[8]/gec0/io63ndb5v0 emc_db[8]/gec0/io80ndb5v0 g2 emc_db[7]/geb1/io62pdb5v0 emc_db[7]/geb1/io79pdb5v0 g3 emc_db[6]/geb0/io62ndb5v0 emc_db[6]/geb0/io79ndb5v0 pin number 256-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-37 g4 gfc2/io67pdb5v0 gfc2/io84pdb5v0 g5 io67ndb5v0 io84ndb5v0 g6 gnd gnd g7 vcc vcc g8 gnd gnd g9 vcc vcc g10 gnd gnd g11 vccfpgaiob 1 vccfpgaiob1 g12 vpp vpp g13 trstb trstb g14 tms tms g15 tck tck g16 gndenvm gndenvm h1 gnd gnd h2 emc_db[5]/g ea1/io61ppb5v0 emc_db[5]/gea1/io78ppb5v0 h3 vccfpgaiob5 vccfpgaiob5 h4 emc_db[1]/geb2/io59pdb5v0 emc_db[1]/geb2/io76pdb5v0 h5 emc_db[0]/gea2/io59ndb5v0 emc_db[0]/gea2/io76ndb5v0 h6 vccfpgaiob5 vccfpgaiob5 h7 gnd gnd h8 vcc vcc h9 gnd gnd h10 vcc vcc h11 gnd gnd h12 vjtag vjtag h13 tdo tdo h14 tdi tdi h15 jtagsel jtagsel h16 gnd gnd j1 emc_db[4]/gea0/io61npb5v0 emc_db[4]/gea0/io78npb5v0 j2 emc_db[3]/gec 2/io60pdb5v0 emc_db[3]/gec2/io77pdb5v0 j3 emc_db[2]/io60ndb5v0 emc_db[2]/io77ndb5v0 j4 gndrcosc gndrcosc pin number 256-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
pin descriptions 5-38 revision 5 j5 gndq gndq j6 gnd gnd j7 vcc vcc j8 gnd gnd j9 vcc vcc j10 gnd gnd j11 vccmssiob2 vccmssiob2 j12 i2c_0_scl/gpio_23 i2c_0_scl/gpio_23 j13 i2c_0_sda/gpio_22 i2c_0_sda/gpio_22 j14 i2c_1_scl/gpio_31 i2c_1_scl/gpio_31 j15 vccmssiob2 vccmssiob2 j16 i2c_1_sda/gpio_30 i2c_1_sda/gpio_30 k1 mac_mdio/io49rsb4v0 mac_mdio/io58rsb4v0 k2 mac_mdc/io48rsb4v0 mac_mdc/io57rsb4v0 k3 vccmssiob4 vccmssiob4 k4 mss_reset_n mss_reset_n k5 vccrcosc vccrcosc k6 vccmssiob4 vccmssiob4 k7 gnd gnd k8 vcc vcc k9 gnd gnd k10 vcc vcc k11 gnd gnd k12 uart_0_rxd/gpio_21 uart_0_rxd/gpio_21 k13 gnd gnd k14 uart_1_txd/gpio_28 uart_1_txd/gpio_28 k15 uart_1_rxd/gpio_29 uart_1_rxd/gpio_29 k16 uart_0_txd/gpio_20 uart_0_txd/gpio_20 l1 gnd gnd l2 mac_txen/io52rsb4v0 mac_txen/io61rsb4v0 l3 mac_crsdv/io51rsb4v0 mac_crsdv/io60rsb4v0 l4 mac_rxer/io50rsb4v0 mac_rxer/io59rsb4v0 l5 mac_clk mac_clk pin number 256-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-39 l6 gnd gnd l7 vcc vcc l8 gnd gnd l9 vcc vcc l10 gnd gnd l11 vccmssiob2 vccmssiob2 l12 spi_1_do/gpio_24 spi_1_do/gpio_24 l13 spi_1_ss/gpio_27 spi_1_ss/gpio_27 l14 spi_1_clk/gpio_2 6 spi_1_clk/gpio_26 l15 spi_1_di/gpio_25 spi_1_di/gpio_25 l16 gnd gnd m1 mac_txd[0]/io56rsb4v0 mac_txd[0]/io65rsb4v0 m2 mac_txd[1]/io55rsb4v0 mac_txd[1]/io64rsb4v0 m3 mac_rxd[0]/io54rsb4v0 mac_rxd[0]/io63rsb4v0 m4 gnd gnd m5 adc3 adc3 m6 gnd15adc0 gnd15adc0 m7 gnd33adc1 gnd33adc1 m8 gnd33adc1 gnd33adc1 m9 adc4 adc4 m10 gndtm1 gndtm1 m11 tm2 tm2 m12 cm2 cm2 m13 spi_0_ss/gpio_19 spi_0_ss/gpio_19 m14 vccmssiob2 vccmssiob2 m15 spi_0_clk/gpio_18 spi_0_clk/gpio_18 m16 spi_0_di/gpio_17 spi_0_di/gpio_17 n1 mac_rxd[1]/io53rsb4v0 mac_rxd[1]/io62rsb4v0 n2 vccmssiob4 vccmssiob4 n3 vcc15a vcc15a n4 vcc33ap vcc33ap n5 abps3 abps3 n6 tm1 tm1 pin number 256-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
pin descriptions 5-40 revision 5 n7 gnd33adc0 gnd33adc0 n8 vcc33adc1 vcc33adc1 n9 adc5 adc5 n10 cm3 cm3 n11 gndaq gndaq n12 varefout varefout n13 gndsdd1 gndsdd1 n14 vcc33sdd1 vcc33sdd1 n15 gnd gnd n16 spi_0_do/gpio_16 spi_0_do/gpio_16 p1 gndsdd0 gndsdd0 p2 vcc33sdd0 vcc33sdd0 p3 vcc33n vcc33n p4 gnda gnda p5 gndaq gndaq p6 cm1 cm1 p7 adc2 adc2 p8 vcc15adc0 vcc15adc0 p9 adc6 adc6 p10 tm3 tm3 p11 gnda gnda p12 vccmainxtal vccmainxtal p13 gndlpxtal gndlpxtal p14 vddbat vddbat p15 ptem ptem p16 ptbase ptbase r1 pcap pcap r2 sdd0 sdd0 r3 abps0 abps0 r4 tm0 tm0 r5 abps2 abps2 r6 adc1 adc1 r7 vcc33adc0 vcc33adc0 pin number 256-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-41 r8 vcc15adc1 vcc15adc1 r9 adc7 adc7 r10 abps7 abps7 r11 abps4 abps4 r12 mainxin mainxin r13 mainxout mainxout r14 lpxin lpxin r15 lpxout lpxout r16 vcc33a vcc33a t1 ncap ncap t2 abps1 abps1 t3 cm0 cm0 t4 gndtm0 gndtm0 t5 adc0 adc0 t6 varef0 varef0 t7 gnd33adc0 gnd33adc0 t8 gnd15adc1 gnd15adc1 t9 varef1 varef1 t10 abps6 abps6 t11 abps5 abps5 t12 sdd1 sdd1 t13 gndvaref gndvaref t14 gndmainxtal gndmainxtal t15 vcclpxtal vcclpxtal t16 pu_n pu_n pin number 256-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely identical functions from density to density. for example, the bank assignment can be different for an i/o, or the f unction might be available only on a larger density device.
pin descriptions 5-42 revision 5 pin number 256-pin fbga a2f060 function a2f200 function a1 gnd gnd a2 vccfpgaiob0 vccfpgaiob0 a3 emc_ab[0]/io04ndb0v0 e mc_ab[0]/io04ndb0v0 a4 emc_ab[1]/io04pdb0v0 e mc_ab[1]/io04pdb0v0 a5 gnd gnd a6 emc_ab[3]/io05pdb0v0 e mc_ab[3]/io05pdb0v0 a7 emc_ab[5]/io06pdb0v0 e mc_ab[5]/io06pdb0v0 a8 vccfpgaiob0 vccfpgaiob0 a9 gnd gnd a10 emc_ab[14]/io11ndb0v0 emc_ab[14]/io11ndb0v0 a11 emc_ab[15]/io11pdb0v0 emc_ab[15]/io11pdb0v0 a12 gnd gnd a13 emc_ab[20]/io14ndb0v 0 emc_ab[20]/io14ndb0v0 a14 emc_ab[24]/io16ndb0v 0 emc_ab[24]/io16ndb0v0 a15 vccfpgaiob0 vccfpgaiob0 a16 gnd gnd b1 emc_db[15]/gaa2/io71pdb5v 0 emc_db[15]/gaa2/io71pdb5v0 b2 gnd gnd b3 emc_byten[1]/gac1/ io02pdb0v0 emc_byten[1]/gac1/io02pdb0v0 b4 emc_oen0_n/io03ndb0v0 emc_oen0_n/io03ndb0v0 b5 emc_oen1_n/io03pdb0v0 emc_oen1_n/io03pdb0v0 b6 emc_ab[2]/io05ndb0v0 e mc_ab[2]/io05ndb0v0 b7 emc_ab[4]/io06ndb0v0 e mc_ab[4]/io06ndb0v0 b8 emc_ab[9]/io08pdb0v0 e mc_ab[9]/io08pdb0v0 b9 emc_ab[12]/io10ndb0v0 emc_ab[12]/io10ndb0v0 b10 emc_ab[13]/io10pdb0 v0 emc_ab[13]/io10pdb0v0 b11 emc_ab[16]/io12ndb0v0 emc_ab[16]/io12ndb0v0 b12 emc_ab[18]/io13ndb0v 0 emc_ab[18]/io13ndb0v0 b13 emc_ab[21]/io14pdb0 v0 emc_ab[21]/io14pdb0v0 b14 emc_ab[25]/io16pdb0 v0 emc_ab[25]/io16pdb0v0 b15 gnd gnd b16 gndq gndq c1 emc_db[14]/gab2/io71ndb5v0 e mc_db[14]/gab2/io71ndb5v0 note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-43 c2 vccpll vccpll c3 emc_byten[0]/gac0/io02ndb0v0 emc_byten[0]/gac0/io02ndb0v0 c4 vccfpgaiob0 vccfpgaiob0 c5 emc_cs0_n/gab0/io01ndb0v0 emc_cs0_n/gab0/io01ndb0v0 c6 emc_cs1_n/gab1/io01pdb0v0 emc_cs1_n/g ab1/io01pdb0v0 c7 gnd gnd c8 emc_ab[8]/io08ndb0v0 emc_ab[8]/io08ndb0v0 c9 emc_ab[11]/io09pdb0v0 emc_ab[11]/io09pdb0v0 c10 vccfpgaiob0 vccfpgaiob0 c11 emc_ab[17]/io12pdb0 v0 emc_ab[17]/io12pdb0v0 c12 emc_ab[19]/io13pdb0 v0 emc_ab[19]/io13pdb0v0 c13 gnd gnd c14 gba2/io20ppb1v0 gba2/io20ppb1v0 c15 gca2/io23pdb1v0 gca2/io23pdb1v0 c16 io23ndb1v0 io23ndb1v0 d1 vccfpgaiob5 vccfpgaiob5 d2 vcompla vcompla d3 gnd gnd d4 gndq gndq d5 emc_clk/gaa0/io00ndb0v0 emc_clk/gaa0/io00ndb0v0 d6 emc_rw_n/gaa1/io00pdb0v 0 emc_rw_n/gaa1/io00pdb0v0 d7 emc_ab[6]/io07ndb0v0 emc_ab[6]/io07ndb0v0 d8 emc_ab[7]/io07pdb0v0 e mc_ab[7]/io07pdb0v0 d9 emc_ab[10]/io09ndb0v0 emc_ab[10]/io09ndb0v0 d10 emc_ab[22]/io15ndb0v0 emc_ab[22]/io15ndb0v0 d11 emc_ab[23]/io15pdb0 v0 emc_ab[23]/io15pdb0v0 d12 gndq gndq d13 gbb2/io20npb1v 0 gbb2/io20npb1v0 d14 gcb2/io24pdb1v0 gcb2/io24pdb1v0 d15 io24ndb1v0 io24ndb1v0 d16 vccfpgaiob1 vccfpgaiob1 e1 emc_db[13]/gac2/io70pdb5v0 emc_db[13]/gac2/io70pdb5v0 e2 emc_db[12]/io70ndb5v0 emc_db[12]/io70ndb5v0 pin number 256-pin fbga a2f060 function a2f200 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-44 revision 5 e3 gfa2/io68pdb5v 0 gfa2/io68pdb5v0 e4 emc_db[10]/io69npb5v0 emc_db[10]/io69npb5v0 e5 gndq gndq e6 gnd gnd e7 vccfpgaiob0 vccfpgaiob0 e8 gnd gnd e9 vccfpgaiob0 vccfpgaiob0 e10 gnd gnd e11 vccfpgaiob0 vccfpgaiob0 e12 gca1/io28pdb1v0 gca1/io28pdb1v0 e13 vccfpgaiob1 vccfpgaiob1 e14 gcb1/io27pdb1v0 gcb1/io27pdb1v0 e15 gdc1/io29pdb1v0 gdc1/io29pdb1v0 e16 gdc0/io29ndb1v0 gdc0/io29ndb1v0 f1 emc_db[9]/gec1/io 63pdb5v0 emc_db[9 ]/gec1/io63pdb5v0 f2 gnd gnd f3 gfb2/io68ndb5v0 gfb2/io68ndb5v0 f4 vccfpgaiob5 vccfpgaiob5 f5 emc_db[11]/io69ppb5v0 emc_db[11]/io69ppb5v0 f6 vccfpgaiob5 vccfpgaiob5 f7 gnd gnd f8 vcc vcc f9 gnd gnd f10 vcc vcc f11 gnd gnd f12 gca0/io28ndb1v 0 gca0/io28ndb1v0 f13 gndq gndq f14 gcb0/io27ndb1v 0 gcb0/io27ndb1v0 f15 gnd gnd f16 vccenvm vccenvm g1 emc_db[8]/gec0/io63ndb5v0 emc_db[8]/gec0/io63ndb5v0 g2 emc_db[7]/geb1/io62pdb5v0 emc_db[7]/geb1/io62pdb5v0 g3 emc_db[6]/geb0/io62ndb5v 0 emc_db[6]/geb0/io62ndb5v0 pin number 256-pin fbga a2f060 function a2f200 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-45 g4 gfc2/io67pdb5v0 gfc2/io67pdb5v0 g5 io67ndb5v0 io67ndb5v0 g6 gnd gnd g7 vcc vcc g8 gnd gnd g9 vcc vcc g10 gnd gnd g11 vccfpgaiob1 vccfpgaiob1 g12 vpp vpp g13 trstb trstb g14 tms tms g15 tck tck g16 gndenvm gndenvm h1 gnd gnd h2 emc_db[5]/gea1/io61ppb5v0 em c_db[5]/gea1 /io61ppb5v0 h3 vccfpgaiob5 vccfpgaiob5 h4 emc_db[1]/geb2/io59pdb5v0 emc_db[1]/geb2/io59pdb5v0 h5 emc_db[0]/gea2/io59ndb5v0 emc_db[0]/gea2/io59ndb5v0 h6 vccfpgaiob5 vccfpgaiob5 h7 gnd gnd h8 vcc vcc h9 gnd gnd h10 vcc vcc h11 gnd gnd h12 vjtag vjtag h13 tdo tdo h14 tdi tdi h15 jtagsel jtagsel h16 gnd gnd j1 emc_db[4]/gea0/io61npb5v0 emc_db[4]/gea0/io61npb5v0 j2 emc_db[3]/gec2/io 60pdb5v0 emc_db[3 ]/gec2/io60pdb5v0 j3 emc_db[2]/io60ndb5v0 emc_db[2]/io60ndb5v0 j4 gndrcosc gndrcosc pin number 256-pin fbga a2f060 function a2f200 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-46 revision 5 j5 gndq gndq j6 gnd gnd j7 vcc vcc j8 gnd gnd j9 vcc vcc j10 gnd gnd j11 vccmssiob2 vccmssiob2 j12 i2c_0_scl/gpio_23 i2c_0_scl/gpio_23 j13 i2c_0_sda/gpio_22 i2c_0_sda/gpio_22 j14 i2c_1_scl/gpio_31 i2c_1_scl/gpio_31 j15 vccmssiob2 vccmssiob2 j16 i2c_1_sda/gpio_30 i2c_1_sda/gpio_30 k1 io49rsb4v0 mac_mdio/io49rsb4v0 k2 io48rsb4v0 mac_mdc/io48rsb4v0 k3 vccmssiob4 vccmssiob4 k4 mss_reset_n mss_reset_n k5 vccrcosc vccrcosc k6 vccmssiob4 vccmssiob4 k7 gnd gnd k8 vcc vcc k9 gnd gnd k10 vcc vcc k11 gnd gnd k12 uart_0_rxd/gpio_21 uart_0_rxd/gpio_21 k13 gnd gnd k14 uart_1_txd/gpio_28 uart_1_txd/gpio_28 k15 uart_1_rxd/gpio_29 uart_1_rxd/gpio_29 k16 uart_0_txd/gpio_20 uart_0_txd/gpio_20 l1 gnd gnd l2 io52rsb4v0 mac_txen/io52rsb4v0 l3 io51rsb4v0 mac_crsdv/io51rsb4v0 l4 io50rsb4v0 mac_rxer/io50rsb4v0 l5 nc mac_clk pin number 256-pin fbga a2f060 function a2f200 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-47 l6 gnd gnd l7 vcc vcc l8 gnd gnd l9 vcc vcc l10 gnd gnd l11 vccmssiob2 vccmssiob2 l12 spi_1_do/gpio_24 spi_1_do/gpio_24 l13 spi_1_ss/gpio _27 spi_1_ss/gpio_27 l14 spi_1_clk/gpio_2 6 spi_1_clk/gpio_26 l15 spi_1_di/gpio_2 5 spi_1_di/gpio_25 l16 gnd gnd m1 io56rsb4v0 mac_txd[0]/io56rsb4v0 m2 io55rsb4v0 mac_txd[1]/io55rsb4v0 m3 io54rsb4v0 mac_rxd[0]/io54rsb4v0 m4 gnd gnd m5 nc adc3 m6 nc gnd15adc0 m7 gnd33adc1 gnd33adc1 m8 gnd33adc1 gnd33adc1 m9 adc4 adc4 m10 gndtm1 gndtm1 m11 tm2 (adc) tm2 m12 cm2 (adc) cm2 m13 spi_0_ss/gpio_19 spi_0_ss/gpio_19 m14 vccmssiob2 vccmssiob2 m15 spi_0_clk/gpio_1 8 spi_0_clk/gpio_18 m16 spi_0_di/gpio_1 7 spi_0_di/gpio_17 n1 io53rsb4v0 mac_rxd[1]/io53rsb4v0 n2 vccmssiob4 vccmssiob4 n3 vcc15a vcc15a n4 vcc33ap vcc33ap n5 nc abps3 n6 nc tm1 pin number 256-pin fbga a2f060 function a2f200 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-48 revision 5 n7 nc gnd33adc0 n8 vcc33adc1 vcc33adc1 n9 adc5 adc5 n10 cm3 cm3 n11 gndaq gndaq n12 varefout varefout n13 nc gndsdd1 n14 nc vcc33sdd1 n15 gnd gnd n16 spi_0_do/gpio_16 spi_0_do/gpio_16 p1 gndsdd0 gndsdd0 p2 vcc33sdd0 vcc33sdd0 p3 vcc33n vcc33n p4 gnda gnda p5 gndaq gndaq p6 nc cm1 p7 nc adc2 p8 nc vcc15adc0 p9 adc6 adc6 p10 tm3 tm3 p11 gnda gnda p12 vccmainxtal vccmainxtal p13 gndlpxtal gndlpxtal p14 vddbat vddbat p15 ptem ptem p16 ptbase ptbase r1 pcap pcap r2 sdd0 sdd0 r3 nc abps0 r4 nc tm0 r5 nc abps2 r6 nc adc1 r7 nc vcc33adc0 pin number 256-pin fbga a2f060 function a2f200 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-49 r8 vcc15adc1 vcc15adc1 r9 adc7 adc7 r10 abps7 abps7 r11 nc abps4 r12 mainxin mainxin r13 mainxout mainxout r14 lpxin lpxin r15 lpxout lpxout r16 vcc33a vcc33a t1 ncap ncap t2 nc abps1 t3 nc cm0 t4 nc gndtm0 t5 nc adc0 t6 nc varef0 t7 nc gnd33adc0 t8 gnd15adc1 gnd15adc1 t9 varef1 varef1 t10 abps6 abps6 t11 nc abps5 t12 nc sdd1 t13 gndvaref gndvaref t14 gndmainxtal gndmainxtal t15 vcclpxtal vcclpxtal t16 pu_n pu_n pin number 256-pin fbga a2f060 function a2f200 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
484-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner
smartfusion intelligent mixed signal fpgas revision 5 5-51 pin number 484-pin fbga a2f200 function a2f500 function a1 gnd gnd a2 nc nc a3 nc nc a4 gnd gnd a5 emc_cs0_n/gab0/io01ndb0v0 emc_cs0_n/gab0/io05ndb0v0 a6 emc_cs1_n/gab1/io01pdb0v0 emc_cs1_n/g ab1/io05pdb0v0 a7 gnd gnd a8 emc_ab[0]/io04ndb0v0 emc_ab[0]/io06ndb0v0 a9 emc_ab[1]/io04pdb0v0 emc_ab[1]/io06pdb0v0 a10 gnd gnd a11 nc nc a12 emc_ab[7]/io07pdb0v0 emc_ab[7]/io12pdb0v0 a13 gnd gnd a14 emc_ab[12]/io10ndb0v0 emc_ab[12]/io14ndb0v0 a15 emc_ab[13]/io10pdb0v0 emc_ab[13]/io14pdb0v0 a16 gnd gnd a17 nc io16ndb0v0 a18 nc io16pdb0v0 a19 gnd gnd a20 nc nc a21 nc nc a22 gnd gnd aa1 gpio_4/io43rsb4v0 gpio_4/io52rsb4v0 aa2 gpio_12/io37rsb4v0 gpio_12/io46rsb4v0 aa3 mac_mdc/io48rsb4v0 mac_mdc/io57rsb4v0 aa4 mac_rxer/io50rsb4v0 mac_rxer/io59rsb4v0 aa5 mac_txd[0]/io56rsb4v0 mac_txd[0]/io65rsb4v0 aa6 abps0 abps0 aa7 tm1 tm1 aa8 adc1 adc1 aa9 gnd15adc1 gnd15adc1 aa10 gnd33adc1 gnd33adc1 aa11 cm3 cm3 aa12 gndtm1 gndtm1 aa13 nc adc10 aa14 nc adc9 note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-52 revision 5 aa15 nc gnd15adc2 aa16 mainxin mainxin aa17 mainxout mainxout aa18 lpxin lpxin aa19 lpxout lpxout aa20 nc nc aa21 nc nc aa22 spi_1_clk/gpio_26 spi_1_clk/gpio_26 ab1 gnd gnd ab2 gpio_13/io36rsb4v0 gpio_13/io45rsb4v0 ab3 gpio_14/io35rsb4v0 gpio_14/io44rsb4v0 ab4 gnd gnd ab5 pcap pcap ab6 ncap ncap ab7 abps3 abps3 ab8 adc3 adc3 ab9 gnd15adc0 gnd15adc0 ab10 vcc33adc1 vcc33adc1 ab11 varef1 varef1 ab12 tm2 tm2 ab13 cm2 cm2 ab14 abps4 abps4 ab15 gndaq gndaq ab16 gndmainxtal gndmainxtal ab17 gndlpxtal gndlpxtal ab18 vcclpxtal vcclpxtal ab19 vddbat vddbat ab20 ptbase ptbase ab21 nc nc ab22 gnd gnd b1 emc_db[15]/gaa2/io71pdb5v0 emc_db[15]/gaa2/io88pdb5v0 b2 gnd gnd b3 nc nc b4 nc nc b5 vccfpgaiob0 vccfpgaiob0 b6 emc_rw_n/gaa1/io00pdb0v0 emc_rw_n/gaa1/io02pdb0v0 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-53 b7 nc io04ppb0v0 b8 vccfpgaiob0 vccfpgaiob0 b9 emc_byten[0]/gac 0/io02ndb0v0 emc_byten[0]/g ac0/io07ndb0v0 b10 emc_ab[2]/io05ndb0v0 emc_ab[2]/io09ndb0v0 b11 emc_ab[3]/io05pdb0v0 emc_ab[3]/io09pdb0v0 b12 emc_ab[6]/io07ndb0v0 emc_ab[6]/io12ndb0v0 b13 emc_ab[14]/io11ndb0v0 emc_ab[14]/io15ndb0v0 b14 emc_ab[15]/io11pdb0v0 emc_ab[15]/io15pdb0v0 b15 vccfpgaiob0 vccfpgaiob0 b16 emc_ab[18]/io13ndb0v0 emc_ab[18]/io18ndb0v0 b17 emc_ab[19]/io13pdb0v0 emc_ab[19]/io18pdb0v0 b18 vccfpgaiob0 vccfpgaiob0 b19 gbb0/io18ndb0v0 gbb0/io24ndb0v0 b20 gbb1/io18pdb0v0 gbb1/io24pdb0v0 b21 gnd gnd b22 gba2/io20pdb1v0 gba2/io27pdb1v0 c1 emc_db[14]/gab2/io71ndb5v0 emc_db[14]/gab2/io88ndb5v0 c2 nc nc c3 nc nc c4 nc io01ndb0v0 c5 nc io01pdb0v0 c6 emc_clk/gaa0/io00ndb0v0 emc_clk/gaa0/io02ndb0v0 c7 nc io03ppb0v0 c8 nc io04npb0v0 c9 emc_byten[1]/gac1/io02pdb0v0 emc_byten[1]/gac1/io07pdb0v0 c10 emc_oen1_n/io03pdb0v0 emc_oen1_n/io08pdb0v0 c11 gnd gnd c12 vccfpgaiob0 vccfpgaiob0 c13 emc_ab[8]/io08ndb0v0 emc_ab[8]/io13ndb0v0 c14 emc_ab[16]/io12ndb0v0 emc_ab[16]/io17ndb0v0 c15 emc_ab[17]/io12pdb0v0 emc_ab[17]/io17pdb0v0 c16 emc_ab[24]/io16ndb0v0 emc_ab[24]/io20ndb0v0 c17 emc_ab[22]/io15ndb0v0 emc_ab[22]/io19ndb0v0 c18 emc_ab[23]/io15pdb0v0 emc_ab[23]/io19pdb0v0 c19 gba0/io19npb0v0 gba0/io23npb0v0 c20 nc nc pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-54 revision 5 c21 gbc2/io21pdb1v0 gbc2/io30pdb1v0 c22 gbb2/io20ndb1v0 gbb2/io27ndb1v0 d1 gnd gnd d2 emc_db[12]/io70ndb5v0 emc_db[12]/io87ndb5v0 d3 emc_db[13]/gac2/io70pdb5v0 emc_db[13]/gac2/io87pdb5v0 d4 nc nc d5 nc nc d6 gnd gnd d7 nc io00npb0v0 d8 nc io03npb0v0 d9 gnd gnd d10 emc_oen0_n/io03ndb0v0 emc_oen0_n/io08ndb0v0 d11 emc_ab[10]/io09ndb0v0 emc_ab[10]/io11ndb0v0 d12 emc_ab[11]/io09pdb0v0 emc_ab[11]/io11pdb0v0 d13 emc_ab[9]/io08pdb0v0 emc_ab[9]/io13pdb0v0 d14 gnd gnd d15 gbc1/io17ppb0v0 gbc1/io22ppb0v0 d16 emc_ab[25]/io16pdb0v0 emc_ab[25]/io20pdb0v0 d17 gnd gnd d18 gba1/io19ppb0v0 gba1/io23ppb0v0 d19 nc nc d20 nc nc d21 io21ndb1v0 io30ndb1v0 d22 gnd gnd e1 gfc2/io67ppb5v0 gfc2/io84ppb5v0 e2 vccfpgaiob5 vccfpgaiob5 e3 gfa2/io68pdb5v0 gfa2/io85pdb5v0 e4 gnd gnd e5 nc nc e6 gndq gndq e7 vccfpgaiob0 vccfpgaiob0 e8 nc io00ppb0v0 e9 nc nc e10 vccfpgaiob0 vccfpgaiob0 e11 emc_ab[4]/io06ndb0v0 emc_ab[4]/io10ndb0v0 e12 emc_ab[5]/io06pdb0v0 emc_ab[5]/io10pdb0v0 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-55 e13 vccfpgaiob0 vccfpgaiob0 e14 gbc0/io17npb0v0 gbc0/io22npb0v0 e15 nc nc e16 vccfpgaiob0 vccfpgaiob0 e17 nc vcompla1 e18 nc io25npb1v0 e19 gnd gnd e20 nc nc e21 vccfpgaiob1 vccfpgaiob1 e22 io22ndb1v0 io32ndb1v0 f1 gfb1/io65ppb5v0 gfb1/io82ppb5v0 f2 io67npb5v0 io84npb5v0 f3 gfb2/io68ndb5v0 gfb2/io85ndb5v0 f4 emc_db[10]/io69npb5v0 emc_db[10]/io86npb5v0 f5 vccfpgaiob5 vccfpgaiob5 f6 vccpll vccpll0 f7 vcompla vcompla0 f8 nc nc f9 nc nc f10 nc nc f11 nc nc f12 nc nc f13 emc_ab[20]/io14ndb0v0 emc_ab[20]/io21ndb0v0 f14 emc_ab[21]/io14pdb0v0 emc_ab[21]/io21pdb0v0 f15 gndq gndq f16 nc vccpll1 f17 nc io25ppb1v0 f18 vccfpgaiob1 vccfpgaiob1 f19 io23ndb1v0 io28ndb1v0 f20 nc io31pdb1v0 f21 nc io31ndb1v0 f22 io22pdb1v0 io32pdb1v0 g1 gnd gnd g2 gfb0/io65npb5v0 gfb0/io82npb5v0 g3 emc_db[9]/gec1/io63pdb5v0 emc_db[9]/gec 1/io80pdb5v0 g4 gfc1/io66ppb5v0 gfc1/io83ppb5v0 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-56 revision 5 g5 emc_db[11]/io69ppb5v0 emc_db[11]/io86ppb5v0 g6 gndq gndq g7 nc nc g8 gnd gnd g9 vccfpgaiob0 vccfpgaiob0 g10 gnd gnd g11 vccfpgaiob0 vccfpgaiob0 g12 gnd gnd g13 vccfpgaiob0 vccfpgaiob0 g14 gnd gnd g15 vccfpgaiob0 vccfpgaiob0 g16 gndq gndq g17 nc io26pdb1v0 g18 nc io26ndb1v0 g19 gca2/io23pdb1v0 gca2/io28pdb1v0 g20 io24ndb1v0 io33ndb1v0 g21 gcb2/io24pdb1v0 gcb2/io33pdb1v0 g22 gnd gnd h1 emc_db[7]/geb1/io62pdb5v0 emc_db[7]/geb1/io79pdb5v0 h2 vccfpgaiob5 vccfpgaiob5 h3 emc_db[8]/gec0/io63ndb5v0 emc_db[8]/gec0/io80ndb5v0 h4 gnd gnd h5 gfc0/io66npb5v0 gfc0/io83npb5v0 h6 gfa1/io64pdb5v0 gfa1/io81pdb5v0 h7 gnd gnd h8 vcc vcc h9 gnd gnd h10 vcc vcc h11 gnd gnd h12 vcc vcc h13 gnd gnd h14 vcc vcc h15 gnd gnd h16 vccfpgaiob1 vccfpgaiob1 h17 io25ndb1v0 io29ndb1v0 h18 gcc2/io25pdb1v0 gcc2/io29pdb1v0 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-57 h19 gnd gnd h20 gcc0/io26npb1v0 gcc0/io35npb1v0 h21 vccfpgaiob1 vccfpgaiob1 h22 gcb0/io27ndb1v0 gcb0/io34ndb1v0 j1 emc_db[6]/geb0/io62ndb5v0 emc_db[6]/geb0/io79ndb5v0 j2 emc_db[5]/gea1/io61pdb5v0 emc_db[5]/gea1/io78pdb5v0 j3 emc_db[4]/gea0/io61ndb5v0 emc_db[4]/gea0/io78ndb5v0 j4 emc_db[3]/gec2/io60ppb5v0 emc_db[3]/gec 2/io77ppb5v0 j5 vccfpgaiob5 vccfpgaiob5 j6 gfa0/io64ndb5v0 gfa0/io81ndb5v0 j7 vccfpgaiob5 vccfpgaiob5 j8 gnd gnd j9 vcc vcc j10 gnd gnd j11 vcc vcc j12 gnd gnd j13 vcc vcc j14 gnd gnd j15 vcc vcc j16 gnd gnd j17 nc io37pdb1v0 j18 vccfpgaiob1 vccfpgaiob1 j19 gca0/io28ndb1v0 gca0/io36ndb1v0 j20 gca1/io28pdb1v0 gca1/io36pdb1v0 j21 gcc1/io26ppb1v0 gcc1/io35ppb1v0 j22 gcb1/io27pdb1v0 gcb1/io34pdb1v0 k1 gnd gnd k2 emc_db[0]/gea2/io59ndb5v0 emc_db[0]/gea2/io76ndb5v0 k3 emc_db[1]/geb2/io59pdb5v0 emc_db[1]/geb2/io76pdb5v0 k4 nc io74ppb5v0 k5 emc_db[2]/io60npb5v0 emc_db[2]/io77npb5v0 k6 nc io75pdb5v0 k7 gnd gnd k8 vcc vcc k9 gnd gnd k10 vcc vcc pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-58 revision 5 k11 gnd gnd k12 vcc vcc k13 gnd gnd k14 vcc vcc k15 gnd gnd k16 vccfpgaiob1 vccfpgaiob1 k17 nc io37ndb1v0 k18 gda1/io31pdb1v0 gda1/io40pdb1v0 k19 gda0/io31ndb1v0 gda0/io40ndb1v0 k20 gdc1/io29pdb1v0 gdc1/io38pdb1v0 k21 gdc0/io29ndb1v0 gdc0/io38ndb1v0 k22 gnd gnd l1 nc io73pdb5v0 l2 nc io73ndb5v0 l3 nc io72ppb5v0 l4 gnd gnd l5 nc io74npb5v0 l6 nc io75ndb5v0 l7 vccfpgaiob5 vccfpgaiob5 l8 gnd gnd l9 vcc vcc l10 gnd gnd l11 vcc vcc l12 gnd gnd l13 vcc vcc l14 gnd gnd l15 vcc vcc l16 gnd gnd l17 gndq gndq l18 gda2/io33ndb1v0 gda2/io42ndb1v0 l19 vccfpgaiob1 vccfpgaiob1 l20 gdb1/io30pdb1v0 gdb1/io39pdb1v0 l21 gdb0/io30ndb1v0 gdb0/io39ndb1v0 l22 gdc2/io32pdb1v0 gdc2/io41pdb1v0 m1 nc io71pdb5v0 m2 nc io71ndb5v0 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-59 m3 vccfpgaiob5 vccfpgaiob5 m4 nc io72npb5v0 m5 gndq gndq m6 nc io68pdb5v0 m7 gnd gnd m8 vcc vcc m9 gnd gnd m10 vcc vcc m11 gnd gnd m12 vcc vcc m13 gnd gnd m14 vcc vcc m15 gnd gnd m16 vccfpgaiob1 vccfpgaiob1 m17 nc nc m18 gdb2/io33pdb1v0 gdb2/io42pdb1v0 m19 vjtag vjtag m20 gnd gnd m21 vpp vpp m22 io32ndb1v0 io41ndb1v0 n1 gnd gnd n2 nc io70pdb5v0 n3 nc io70ndb5v0 n4 vccrcosc vccrcosc n5 vccfpgaiob5 vccfpgaiob5 n6 nc io68ndb5v0 n7 vccfpgaiob5 vccfpgaiob5 n8 gnd gnd n9 vcc vcc n10 gnd gnd n11 vcc vcc n12 gnd gnd n13 vcc vcc n14 gnd gnd n15 vcc vcc n16 nc gnd pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-60 revision 5 n17 nc nc n18 vccfpgaiob1 vccfpgaiob1 n19 vccenvm vccenvm n20 gndenvm gndenvm n21 nc nc n22 gnd gnd p1 nc io69ndb5v0 p2 nc io69pdb5v0 p3 gndrcosc gndrcosc p4 gnd gnd p5 nc nc p6 nc nc p7 gnd gnd p8 vcc vcc p9 gnd gnd p10 vcc vcc p11 gnd gnd p12 vcc vcc p13 gnd gnd p14 vcc vcc p15 gnd gnd p16 vccfpgaiob1 vccfpgaiob1 p17 tdi tdi p18 tck tck p19 gnd gnd p20 tms tms p21 tdo tdo p22 trstb trstb r1 mss_reset_n mss_reset_n r2 vccfpgaiob5 vccfpgaiob5 r3 gpio_1/io46rsb4v0 gpio_1/io55rsb4v0 r4 nc nc r5 nc nc r6 nc nc r7 nc nc r8 gnd gnd pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-61 r9 vcc vcc r10 gnd gnd r11 vcc vcc r12 gnd gnd r13 vcc vcc r14 gnd gnd r15 vcc vcc r16 jtagsel jtagsel r17 nc nc r18 nc nc r19 nc nc r20 nc nc r21 vccfpgaiob1 vccfpgaiob1 r22 nc nc t1 gnd gnd t2 vccmssiob4 vccmssiob4 t3 gpio_8/io39rsb4v0 gpio_8/io48rsb4v0 t4 gpio_11/io57rsb4v0 gpio_11/io66rsb4v0 t5 gnd gnd t6 mac_clk mac_clk t7 vccmssiob4 vccmssiob4 t8 vcc33sdd0 vcc33sdd0 t9 vcc15a vcc15a t10 gndaq gndaq t11 gnd33adc0 gnd33adc0 t12 adc7 adc7 t13 nc tm4 t14 nc varef2 t15 varefout varefout t16 vccmssiob2 vccmssiob2 t17 spi_1_do/gpio_24 spi_1_do/gpio_24 t18 gnd gnd t19 nc nc t20 nc nc t21 vccmssiob2 vccmssiob2 t22 gnd gnd pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-62 revision 5 u1 gnd gnd u2 gpio_5/io42rsb4v0 gpio_5/io51rsb4v0 u3 gpio_10/io58rsb4v0 gpio_10/io67rsb4v0 u4 vccmssiob4 vccmssiob4 u5 mac_rxd[1]/io53rsb4v0 mac_rxd[1]/io62rsb4v0 u6 nc nc u7 vcc33ap vcc33ap u8 vcc33n vcc33n u9 cm1 cm1 u10 varef0 varef0 u11 gnd33adc1 gnd33adc1 u12 adc4 adc4 u13 nc gndtm2 u14 nc adc11 u15 gndvaref gndvaref u16 vcc33sdd1 vcc33sdd1 u17 spi_0_do/gpio_16 spi_0_do/gpio_16 u18 uart_0_rxd/gpio_21 uart_0_rxd/gpio_21 u19 vccmssiob2 vccmssiob2 u20 i2c_1_scl/gpio_31 i2c_1_scl/gpio_31 u21 i2c_0_scl/gpio_23 i2c_0_scl/gpio_23 u22 gnd gnd v1 gpio_0/io47rsb4v0 gpio_0/io56rsb4v0 v2 gpio_6/io41rsb4v0 gpio_6/io50rsb4v0 v3 gpio_9/io38rsb4v0 gpio_9/io47rsb4v0 v4 mac_mdio/io49rsb4v0 mac_mdio/io58rsb4v0 v5 mac_rxd[0]/io54rsb4v0 mac_rxd[0]/io63rsb4v0 v6 gnd gnd v7 sdd0 sdd0 v8 abps1 abps1 v9 adc2 adc2 v10 vcc33adc0 vcc33adc0 v11 adc6 adc6 v12 adc5 adc5 v13 abps5 abps5 v14 nc adc8 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
smartfusion intelligent mixed signal fpgas revision 5 5-63 v15 nc gnd33adc2 v16 nc nc v17 gnd gnd v18 spi_0_di/gpio_17 spi_0_di/gpio_17 v19 spi_1_di/gpio_25 spi_1_di/gpio_25 v20 uart_1_txd/gpio_28 uart_1_txd/gpio_28 v21 i2c_0_sda/gpio_22 i2c_0_sda/gpio_22 v22 i2c_1_sda/gpio_30 i2c_1_sda/gpio_30 w1 gpio_2/io45rsb4v0 gpio_2/io54rsb4v0 w2 gpio_7/io40rsb4v0 gpio_7/io49rsb4v0 w3 gnd gnd w4 mac_crsdv/io51rsb4v0 mac_crsdv/io60rsb4v0 w5 mac_txd[1]/io55rsb4v0 mac_txd[1]/io64rsb4v0 w6 nc sdd2 w7 gnda gnda w8 tm0 tm0 w9 abps2 abps2 w10 gnd33adc0 gnd33adc0 w11 vcc15adc1 vcc15adc1 w12 abps6 abps6 w13 nc cm4 w14 nc abps9 w15 nc vcc33adc2 w16 gnda gnda w17 pu_n pu_n w18 gndsdd1 gndsdd1 w19 spi_0_clk/gpio_18 spi_0_clk/gpio_18 w20 gnd gnd w21 spi_1_ss/gpio_27 spi_1_ss/gpio_27 w22 uart_1_rxd/gpio_29 uart_1_rxd/gpio_29 y1 gpio_3/io44rsb4v0 gpio_3/io53rsb4v0 y2 vccmssiob4 vccmssiob4 y3 gpio_15/io34rsb4v0 gpio_15/io43rsb4v0 y4 mac_txen/io52rsb4v0 mac_txen/io61rsb4v0 y5 vccmssiob4 vccmssiob4 y6 gndsdd0 gndsdd0 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
pin descriptions 5-64 revision 5 y7 cm0 cm0 y8 gndtm0 gndtm0 y9 adc0 adc0 y10 vcc15adc0 vcc15adc0 y11 abps7 abps7 y12 tm3 tm3 y13 nc abps8 y14 nc gnd33adc2 y15 nc vcc15adc2 y16 vccmainxtal vccmainxtal y17 sdd1 sdd1 y18 ptem ptem y19 vcc33a vcc33a y20 spi_0_ss/gpio_19 spi_0_ss/gpio_19 y21 vccmssiob2 vccmssiob2 y22 uart_0_txd/gpio_20 uart_0_txd/gpio_20 pin number 484-pin fbga a2f200 function a2f500 function note: shading denotes pins that do not have completely i dentical functions from density to density. for example, the bank assignment can be different for an i/o, or the function might be available only on a larger density device.
revision 5 6-1 6 ? datasheet information list of changes the following table lists critical changes that were made in each revision of the smartfusion datasheet. revision changes page revision 5 (december 2010) table 2-2 ? analog maximum ratings was revised. the re commended cm[n] pad voltage (relative to ground) was changed from ?11 to ?0.3 (sar 28219). 2-2 table 2-7 ? temperature and voltage derating factors for timing delays was revised to change the values for 100oc. 2-9 power-down and sleep modes, and all associated notes, were removed from table 2-8 ? quiescent supply current characteristics (sar 29479). idc3 and idc4 were renamed to idc1 and idc2 (sar 29478). these modes are no longer supported. a note was added to the table stating that current monitors and temperature monitors should not be used when power-down and/or sleep mode are required by the application. 2-10 the "power-down and sleep mode implementation" section was deleted (sar 29479). n/a values for pac9 and pac10 for lv ds and lvpecl were revised in ta b l e 2 - 9 ? summary of i/o input buffer power (per pin) ? default i/o software settings and table 2-11 ? summary of i/o output buffer power (per pin) ? default i/o software settings* . 2-10 , 2-11 values for pac1 through pac4, pdc1, and pdc2 were added for a2f500 in table 2-13 ? different components contri buting to dynamic power consumption in smartfusion devices and table 2-14 ? different components contributing to the static power consumption in smartfusion devices 2-12 , 2-13 the equation for "total dynamic power consumption?pdyn" in "soc mode" was revised to add p mss . the "microcontroller subsystem dynamic contribution?pmss" section is new (sar 29462). 2-14 , 2-18 information in table 2-23 ? summary of i/o timing characteristics?software default settings (applicable to fpga i/o banks) and table 2-24 ? summary of i/o timing characteristics?software default settings (applicable to mss i/o banks) was updated. 2-25 available values for the std. speed were added to the timing tables from table 2-37 ? 3.3 v lvttl / 3.3 v lvcmos high slew to table 2-90 ? jtag 1532 (sar 29331). one or more values changed for the ?1 speed in tables covering 3.3 v lvcmos, 2.5 v lvcmos, 1.8 v lvcmos, 1.5 v lvcmos, combinatorial cell propagation delays, and a2f200 global resources. 2-31 to 2-74 table 2-79 ? a2f500 global resource is new. 2-60 table 2-88 ? envm block timing, worst commercial case conditions: tj = 85c, vcc = 1.425 v was revised (sar 27585). 2-73 the programmable analog specifications t ables were revised with updated information. 2-75 to 2-84 table 4-1 ? supported jtag programming hardware was revised by adding a note to indicate "planned support" for several of the items in the table. 4-5
datasheet information 6-2 revision 5 revision 5 (continued) the note on jtagsel in the "in-system programming" section was revised to state that softconsole selects the appropriate tap controller using the ctxselect jtag command. when using softconsole, the state of jtagsel is a "don't care" (sar 29261). 4-5 the "288-pin csp" and "256-pin fbga" pin tables for a2f060 are new, comparing the a2f060 function with the a2f 200 function (sar 29353). 5-25 the "handling when unused" column was removed from the "256-pin fbga" pin table for a2f200 and a2f500 (sar 29691). 5-34 revision 4 (september 2010) table 2-8 ? quiescent supply current characteristics was revised. vccrcosc was moved to a column of its own with new values. vccenvm was added to the table. standby mode for vjtag and vpp was changed from 0 v to n/a. "disable" was changed to "off "in the envm column. the column for rcosc was deleted. 2-10 the "power-down and sleep mode implementation" section was revised to include vccrosc. 2-11 revision 3 (september 2010) the "i/os and operating voltage" section was revised to list "s ingle 3.3 v power supply with on-chip 1.5 v regulator" and "exter nal 1.5 v is allowed" (sar 27663). i the cs288 package was added to the "package i/os: mss + fpga i/os" table (sar 27101), "product ordering codes" table , and "temperature grade offerings" table (sar 27044). the number of direct analog inputs for the fg256 package in a2f060 was changed from 8 to 6. iii , vi , vi two notes were added to the "smartfusion family product table" indicating limitations for features of the a2f500 device: two plls are available in cs 288 and fg484 (one pll in fg256). [adcs, dacs, scbs, compar ators, current monitors, and bipolar high voltage monitors are] available on fg484 only. fg256 and cs288 packages offer the same programmable analog capabilities as a2f200. table cells were merged in rows containing the same values for easier reading (sar 24748). ii the security feature option was added to the "product ordering codes" table. vi in table 2-3 ? recommended operating conditions , the vddbat recommended operating range was changed from "2.97 to 3.63" to "2.7 to 3.63" (sar 25246). recommended operating range was changed to "3.15 to 3.45" for the following voltages: vcc33a vcc33adcx vcc33ap vcc33sddx vccmainxtal vcclpxtal two notes were added to the table (sar 27109): 1. the following 3.3 v supplies should be connected together while following proper noise filtering practices: vcc33a, vcc33adc x, vcc33ap, vcc33s ddx, vccmainxtal, and vcclpxtal. 2. the following 1.5 v supplies should be connected together while following proper noise filtering practices: vcc, vcc15a, and vcc15adcx. 2-3 in table 2-3 ? recommended operating conditions , the description for vcclpxtal was corrected to change "32 hz" to "32 khz" (sar 27110). 2-3 the "power supply sequencing requirement" section is new (sar 27178). 2-4 revision changes page
smartfusion intelligent mixed signal fpgas revision 5 6-3 revision 3 (continued) table 2-8 ? quiescent supply current characteristics was revised to change most on/off entries to voltages. note 5 was added, stating that "on" means proper voltage is applied. the values of 6 a and 16 a were removed for idc1 and idc2 for 3.3 v. a note was added for idc1 and idc2: "power mode and sleep mode are consuming higher current than expected in the current ve rsion of silicon. thes e specifications will be updated when new version of the silicon is available" (sar 27926). 2-10 the "power-down and sleep mode implementation" section is new (sar 27178). 2-11 a note was added to table 2-84 ? smartfusion ccc/pll specification , pertaining to f out_ccc , stating that "one of the ccc outputs (gla0) is used as an mss clock and is limited to 100 mhz (maximum) by software" (sar 26388). 2-63 table 2-88 ? envm block timing, worst commercial case conditions: tj = 85c, vcc = 1.425 v was revised. values were included for a2f200 and a2f500, for ?1 and std. speed grades. a note was added to def ine 6:1:1:1 and 5:1:1:1 (sar 26166). 2-73 the units were corrected (mv instead of v) fo r input referred offset voltage, gdec[1:0] = 00 in table 2-94 ? abps performance specifications (sar 25381). 2-79 the test condition values for operating current (icc33a, typical) were changed in table 2-97 ? voltage regulator (sar 26465). 2-84 figure 2-44 ? typical output voltage was revised to add legends for the three curves, stating the load represented by each (sar 25247). 2-85 the "smartfusion programming" chapter was moved to this document from the smartfusion subsystem microcontro ller user?s guide (sar 26542). the "typical programming and erase times" section was added to this chapter. 4-5 figure 4-1 ? trstb logic was revised to change 1.5 v to "vjtag (1.5 v to 3.3 v nominal)" (sar 24694). 4-6 two notes were added to the "supply pins" table (sar 27109): 1. the following supplies should be connected together while following proper noise filtering practices: vcc33a, vcc33adc x, vcc33ap, vcc33s ddx, vccmainxtal, and vcclpxtal. 2. the following 1.5 v supplies should be connected together while following proper noise filtering practices: vcc, vcc15a, and vcc15adcx. 5-1 the descriptions for the "vcc33n" , "ncap" , and "pcap" pins were revised to include information on what to do if analog scb f eatures and sdds are not used (sar 26744). 5-2 , 5-6 , 5-7 information was added to the "user pins" table regarding tristating of used and unused gpio pins. the io portion of the table was revised to state that unused i/o pins are disabled by libero ide software and include a weak pull-up resistor (sar 26890). information was added regarding behavior of used i/o pins during power-up. 5-5 the type for "emc_rw_n" was changed from in/out to out (sar 25113). 5-10 a note was added to the "analog front-end (afe)" table stating that unused analog inputs should be grounded (sar 26744). 5-12 the "288-pin csp" section is new, with pin tables for a2f200 and a2f500 (sar 27044). 5-16 the "256-pin fbga" pin table was replaced and now includes "handling when unused" information (sar 27709). 5-33 revision changes page
datasheet information 6-4 revision 5 revision 2 (may 2010) embedded nonvolatile flash memory (envm) was changed from "64 to 512 kbytes" to "128 to 512 kbytes" in the "microcontroller subsystem (mss)" section and "smartfusion family product table" (sar 26005). i , ii the main oscillator range of values was changed to "32 khz to 20 mhz" in the "microcontroller subsystem (mss)" section and the "smartfusion family product ta b l e " (sar 24906). i , ii the value for t pd was changed from 50 ns to 15 ns for the high-speed voltage comparators listed in the "analog front-end (afe)" section (sar 26005). i the number of plls for a2f200 was changed from 2 to 1 in the "smartfusion family product table" (sar 25093). ii values for direct analog input, total analog input, and total i/os were updated for the fg256 package, a2f060, in the "package i/os: mss + fpga i/os" table . the max. column was removed from the table (sar 26005). iii the speed grade section of the "product ordering codes" table was revised (sar 25257). vi revision 1 (march 2010) the "product ordering codes" table was revised to add "blank" as an option for lead- free packaging and application (junction temperature range). vi table 2-3 ? recommended operating conditions was revised. ta (ambient temperature) was replaced with t j (junction temperature). 2-3 pdc5 was deleted from table 2-14 ? different components contributing to the static power consumption in smartfusion devices . 2-13 the formulas in the footnotes for table 2-28 ? i/o weak pull-up/pull-down resistances were revised. 2-27 the values for input biased current were revised in table 2-91 ? current monitor performance specification . 2-75 revision 0 (march 2010) the "analog front-end (afe)" section was updated to change the throughput for 10- bit mode from 600 ksps to 550 ksps. i the a2f060 device was added to product information tables. n/a the "product ordering codes" table was updated to removed std. speed and add speed grade 1. pre-production was remo ved from the application ordering code category. vi the "smartfusion block diagram" was revised. iv the "datasheet categories" section was updated, referencing the "smartfusion block diagram" table , which is new. 1-4 , iv the "vcci" parameter was renamed to "vccxxxxiobx." "advanced i/os" were renamed to "fpga i/os." generic pin names that repres ent multiple pins were standardized with a lower case x as a placeholder. for example, varefx designates varef0, varef1, and varef2. modes were renamed as follows: operating mode was renamed to soc mode. 32khz active mode was renamed to standby mode. battery mode was renamed to time keeping mode. table entries have been filled with values as data has become available. n/a revision changes page
smartfusion intelligent mixed signal fpgas revision 5 6-5 revision 0 (continued) table 2-1 ? absolute maximum ratings , table 2-2 ? analog maximum ratings , and table 2-3 ? recommended operating conditions were revised extensively. 2-1 through 2-3 device names were updated in table 2-6 ? package thermal resistance . 2-7 table 2-8 ? quiescent supply current characteristics was revised extensively. 2-10 table 2-10 ? summary of i/o input buffer power (per pin) ? default i/o software settings was revised extensively. 2-11 removed "example of power calculation." n/a table 2-13 ? different components contri buting to dynamic power consumption in smartfusion devices was revised extensively. 2-12 table 2-14 ? different components contributing to the static power consumption in smartfusion devices was revised extensively. 2-13 the "power calculation methodology" section was revised. 2-14 table 2-81 ? electrical characteristics of the rc oscillator was revised extensively. 2-61 table 2-83 ? electrical characteristics of the low power oscillator was revised extensively. 2-62 the parameter t rstbq was changed to t c2cwrh in table 2-85 ? ram4k9 . 2-68 the 12-bit mode row for integral non-linearity was removed from table 2-93 ? adc specifications . the typical value for 10-bit mode was revised. the table note was punctuated correctly to make it clear. 2-77 figure 37-34 ? write access after write onto same address, figure 37-34 ? read access after write onto same address, and figure 37-34 ? write access after read onto same address were deleted. n/a table 2-97 ? voltage regulator was revised extensively. 2-84 the "serial peripheral interface ( spi) characteristics" section and "inter-integrated circuit (i2c) characteristics" section are new. 2-86 , 2-88 "smartfusion development tools" section was replaced with new content. 3-1 the pin description tables were revised by adding additional pins to reflect the pinout for a2f500. 5-1 through 5-14 the descriptions for "gndsdd1" and "vcc33sdd1" were revised. 5-1 , 5-2 the description for "vcc33a" was revised. 5-2 the pin tables for the "256-pin fbga" and "484-pin fbga" were replaced with tables that compare pin functions across densities for each package. 5-33 draft b (december 2009) the "digital i/os" sect ion was renamed to the "i/os and operating voltage" section and information was added regarding digital and analog vcc. i the "smartfusion family product table" and "package i/os: mss + fpga i/os" section were revised. ii the terminology for the analog blocks was changed to "programmable analog," consisting of two blocks: the analog fron t-end and analog compute engine. this is reflected throughout the text and in the "smartfusion block diagram" . iv the "product ordering codes" table was revised to add g as an ordering code for envm size. vi revision changes page
datasheet information 6-6 revision 5 draft b (continued) timing tables were populated with information that has become available for speed grade ?1. n/a all occurrences of the vmv parameter were removed. n/a the sdd[n] voltage parameter was removed from table 2-2 ? analog maximum ratings . 2-2 table 36-4 ? flash programming limits ? retention, storage and operating temperature was replaced with table 2-4 ? fpga and embedded flash programming, storage and operating limits . 2-4 the "thermal characte ristics" section was revised extensively. 2-7 table 2-8 ? quiescent supply current characteristics was revised significantly. 2-10 table 2-13 ? different components contri buting to dynamic power consumption in smartfusion devices and table 2-14 ? different components contributing to the static power consumption in smartfusion devices were updated. 2-12 figure 2-2 ? timing model was updated. 2-19 the temperature associated with the reliability for lvttl/lvcmos in table 2-33 ? i/o input rise time, fall time, and related i/o reliability was changed from 110o to 100o. 2-29 the values in table 2-77 ? combinatorial cell propagation delays were updated. 2-57 table 2-83 ? electrical characteristics of the low power oscillator is new. table 2-82 ? electrical characteristics of the main crystal oscillator was revised. 2-62 table 2-88 ? envm block timing, worst commercial case conditions: tj = 85c, vcc = 1.425 v and table 2-89 ? flashrom access time, worse commercial case conditions: tj = 85c, vcc = 1.425 v are new. 2-73 the performance tables in the "programmable analog sp ecifications" section were revised, including new data available. table 2-96 ? analog sigma-delta dac is new. 2-75 the "256-pin fbga" table for a2f200 is new. 4-15 revision changes page
smartfusion intelligent mixed signal fpgas revision 5 6-7 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "smartfusion device status" table on page iii , is designated as eit her "product brief," "advance," "preliminary," or "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. microsemi soc products group safety critical, life support, and high-reliability applications policy the soc products group products described in this advance status document may not have completed the soc products group?s qualific ation process. products may be amended or enhanced during the product introduction and qualification process, re sulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including a ppropriateness for safety-critical, life-support, and other high-reliability applications. consult the soc products group?s terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available on the soc products group website at http://www.actel.com/documents/ort_report.pdf . microsemi soc products group also offers a variety of enhanced qualification and lot acceptance scre ening procedures. contact your local soc products group sales office for additional reliability information.
51700112-5/3.10 ? 2010 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers the industry?s most comprehensive portfolio of semiconductor technology. committed to solving t he most critical system challenges, microsemi?s products include high-performance, high-reliabilit y analog and rf devices, mixed signal integrated circuits, fpgas and customizable socs, and co mplete subsystems. microsemi serves leading system manufacturers around the world in th e defense, security, aerospace, enterprise, commercial, and industrial markets. learn more at www.microsemi.com . microsemmi corporate headquarters 2381 morse avenue, irvine, ca 92614 phone: 949-221-7100fax: 949-756-0308 www.microsemi.com

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